w65c134s Western Design Center, Inc., w65c134s Datasheet - Page 14

• Manufacturer Part Number: w65c134s
• Description: W65c134s 8-bit Microcontroller
• Manufacturer: Western Design Center, Inc.

1.10
Serial
Data
The W65C134S Microcomputer provides a full duplex Universal Asynchronous Receiver/Transmitter
(UART) with programmable bit rates. The serial I/O functions are controlled by the Asynchronous Control
and Status Register (ACSR). The ACSR bit assignment is shown in Figure 1-9. The serial bit rate is
determined by Timer A for all modes. The maximum data rate using the internal clock is 62.5K bits per
second (PHI2 = 1MHz).
independently enabled or disabled. All transmitter and receiver bit rates will occur at one sixteenth of the
Timer A interval timer rate. Timer A is forced into an interval timer mode whenever the serial I/O is
enabled.
Whenever Timer A is required as a timing source, it must be loaded with the hexadecimal code that
selects the data rate for the serial I/O Port. Refer to Table 1-2 for a table of hexadecimal values that
represent the desired data rate.
W DC Standard UART Features
U
The Transmitter Interrupt is controlled by the Asynchronous Control Status Register bit ACSR1.
IRQAT = ACSR0((ACSR1B)(DATA REGISTER EMPTY) + (ACSR1)(DATA REGISTER AND SHIFT
• 7 or 8 bit data with or without Odd or Even parity.
• The Transmitter has 1 stop bit with parity or 2 stop bits without parity.
• The Receiver requires only 1 stop bit for all modes.
• Both the Receiver and Transmitter have priority encoded interrupts for service routines.
• The Receiver has error detection for parity error, framing error, or over-run error conditions that
• The Receiver Interrupt occurs due to a receiver data register full condition.
• The Transmitter Interrupt can be selected to occur on either the data register empty (end-of-byte
1.10.1 Asynchronous Transmitter Operation
Universal Asynchronous Receiver/Transmitter (UART)
may require re-transmission of the message.
transmission) or both the data register empty and the shift register empty (end-of-message
transmission) condition.
REGISTER EMPTY))
The transmitter operation is controlled by the Asynchronous Control and Status Register
(ACSR). The transmitter automatically adds a start bit, parity bit and one or two stop bits as
defined by the ACSR. A word of transmitted data is 7 or 8 bits of data.
The Transmitter Data Register (ARTD) is located at address $0023 and is loaded on a
write. The Receiver is read at this same address.
Start
Bit
0
Figure 1-7 Asynchronous Transmitter Mode with Parity
The Asynchronous Transmitter and Asynchronous Receiver can be
1
2
3
4
5
6
7
Parity
Bit
Stop
Bit
14