w65c134s Western Design Center, Inc., w65c134s Datasheet - Page 15

• Manufacturer Part Number: w65c134s
• Description: W65c134s 8-bit Microcontroller
• Manufacturer: Western Design Center, Inc.

1.10.2 Asynchronous Receiver Operation
Serial
Data
Note:
1.10.3 Asynchronous Control and Status Register (ACSR)
The receiver and its selected control and status functions are enabled when ACSR5 is set to
a "1". The Receiver Data Register (ARTD) is located at $0023. The data format must have a
start bit, 7 or 8 data bits, and one stop bit or one parity bit and one stop bit. The receiver bit
period is divided into 16 sub-intervals for internal synchronization. The receiver bit stream is
synchronized by the start bit, and a strobe signal is generated at the approximate center of
each incoming bit. The character assembly process does not start if the start bit signal is less
than one-half the bit time after a low level is detected on the Receive Data Input. A framing
error, parity error or an over-run will set ASCR7, the receiver error detection bit. An over-run
condition occurs when the receiver data register has not been read and new data byte is
transferred from the receiver shift register
The receiver requires only one stop bit but the transmitter supplies two stop bits for older
system timing.
A receiver interrupt (IRQAR) is generated whenever the receiver shift register is transferred
to the receiver data register.
The Asynchronous Control and Status Register (ACSR) enables the Receiver and
Transmitter and holds information on communication status error conditions.
Bit assignments and function of the ACSR are as follows:
ACSR0:
ACSR1:
ACSR2:
Start
Bit
T ransmitter Enable.
U
Interrupt (IRQAT), and TXD is enabled on P61 when ACSR0=1. When ACSR0
is cleared, the ACSR1 is cleared, the transmitter will be disabled, the
Transmitter Interrupt will not occur and TXD will be disabled on P61. This bit is
cleared by a RESET.
T ransmitter Interrupt Source Select.
U
occurs due to a Transmitter Data Register Empty condition (end-of-byte
transmission). When ACSR1=1 the Transmitter Interrupt occurs due to both the
Transmitter Data and Shift register empty condition (end-of-message
transmission). The Transmitter Interrupt is cleared by writing to the Transmitter
Data Register ($0023), or by a RESET.
S even or Eight-Bit Data Select.
U
send and receive 7-bit data.
information (one start, 7 data, one parity and one stop or 2 stop bits). The
Receiver receives 9 or 10 bits of information (one start, 7 data, and one stop or
one stop and one parity bits).
0
Figure 1-8 Asynchronous Receiver Data Timing
1
2
U
The Asynchronous Transmitter is enabled, the Transmitter
3
.
U
When ACSR2=0, the Transmitter and Receiver
The Transmitter sends a total of 10 bits of
4
U
When ACSR1=0, the Transmitter Interrupt
5
6
Stop
Bit
Stop
Bit
15