w65c134s Western Design Center, Inc., w65c134s Datasheet - Page 35

• Manufacturer Part Number: w65c134s
• Description: W65c134s 8-bit Microcontroller
• Manufacturer: Western Design Center, Inc.

2.5
Bus Enable and RDY Input (BE)
2.5.1
2.5.2
2.5.3
2.5.4
2.5.5
BE = BE . (RDY + PHI2B) (This logic is on the ICE to provide the emulation interface normally used
for W65C02S systems.)
Notes:
1)
2)
signaling the power-up condition, the processor starts; and if BE was low when RESB
went from low to high, then the Bus Control Register (BCR) bits 0, 3, and 7 (BCR0,
BCR3, and BCR7) are set to 1 (emulation mode).
bus (D0-D7) and WEB.
for DMA (direct memory and I/O access) for emulation purposes. Data from D0-D7 is
written to any register addressed by A0-A15 when WEB is low. Data is read from D0-D7
when WEB is high. The W65C02S is stopped when BE is low.
microprocessor.
address, data BUS and WEB signals. When BE is pulled low in PHI2 high time, the
W65C02S is stopped so that the processor may be single stepped in emulation.
registers or memory. Use this mode for DMA.
write of internal I/O register or memory is output on the
internal data bus may be traced in emulation.
BE controls the address bus, data bus and WEB signals. When RESB goes high
After RESB goes high BE controls the direction of the address bus (A0-A7, A8-A15), data
When BE goes low during PHI2 low time, the address bus and WEB are inputs, providing
When BE is high, the A0-A15, D0-D7 and WEB are controlled by the on-chip
When BE is pulled low during PHI2 high time, BE does not affect the direction of the
Address and WEB are inputs with data bus input except when reading on-chip I/O
W65C02S stopped with RDY function of BE pin. When BCR3=1, the W65C02S read or
Figure 2-3 BE Timing Relative to PHI2
external data bus so that the
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