w65c134s Western Design Center, Inc., w65c134s Datasheet - Page 19

• Manufacturer Part Number: w65c134s
• Description: W65c134s 8-bit Microcontroller
• Manufacturer: Western Design Center, Inc.

1.11.3
SR3 bits SR37, SR36 and SR35 are the Bus Address Register field of the 32-bit message.
All other bits are command, data, or address fields. Reading SR3 clears the read pending
bit SCSR4 and writing SR0 clears the write pending bit SCSR0.
The SIB Control and Status Register (SCSR).
The SIB Control and Status Register (SCSR) is used for controlling the SIB and for
reading the status of the SIB. The SCSR is writable only in the sense that a high
level can be written to bits SCSR0, SCSR2, SCSR6 and SCSR7. Together with the
STATE Register, it gives the state of the SIB controller. Bit SCSR6 is used to enable
PHI2 as the clock source for SCLK, bits SCSR4 and SCSR5 are used for receiving,
bits SCSR0, SCSR1, and SCSR2 are used for sending, and STATE is used for both.
1.11.3.0
1.11.3.1
The SCSR is reset on a system RESET.
SCSR0 is the "write pending" control bit of the SCSR. When SCSR0 is
set to a "1" by the on-chip microprocessor, it means that the processor
wants to send a message. It is set on a write of a "1" to SCSR0 from
the MPU and reset when SR0 is written.
SCSR1 is the "master" status bit of SCSR. When SCSR1 gets set to a
"1" this means that the SIB's microprocessor was requesting master
(SCSR0 was set to a "1") just before the last time mastery changed. If
CHIN (CHain IN) is high as well then this device is master when the
"token" is passed.
Figure 1-11 SR0, SR1, SR2, and SR3 Shift Register
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