w65c134s Western Design Center, Inc., w65c134s Datasheet - Page 23

• Manufacturer Part Number: w65c134s
• Description: W65c134s 8-bit Microcontroller
• Manufacturer: Western Design Center, Inc.

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*2
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The SDAT goes low due to SCSR0 (write pending) set in all devices that are requesting the bus.
The previous master sets SCSR2 (previous master) and sets CHOUT high, all others clear
SCSR2. The next device with CHIN high and SCSR0 set becomes bus master, and clears
CHOUT to low.
The bus master interrupts its MPU and the MPU loads the shift register. Writing to SR0 clears
SCSR0 (write pending) and sends the message. The SIB waits until the shift register SR0 is
written. Any device that has SCSR4 set (read pending), sets SCSR5 (deaf) indicating the MPU
never read the last message sent to it. Reading SR3 clears SCSR4 (read pending).
The 32-bit message is sent by the bus master during states 3-34. The BEGIN low time begins on
the transfer of data to the masters shift register during state 2 and stays low until the first transmit
data bit
data latched on the falling edge of SCLK.
The bus master sets SDAT to '1' signaling the end of transmission.
The receiver device pulls SDAT low signaling the bus master that the message was received. If
the receiving device does not pull SDAT low then the bus master sets SCSR3 (message not
acknowledged) indicating the message was not received, and will interrupt its MPU in the next
state (State 37).
Figure 1-13 Serial Interface Bus (SIB) Message Transmission Timing Diagram
1.11.5
The Bus Address Register (BAR) contains the address that is used by the receive
function logic of the SIB to compare against the "address field" (SR37,SR36 and SR35)
of the Shift Register incoming data. When the BAR address matches the "address field"
of the Shift Register the host is interrupted indicating that a "message has been
received".
time in state 3. The output data is transferred on the rising edge of SCLK with the input
Bus Address Register (BAR)
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