w65c134s Western Design Center, Inc., w65c134s Datasheet - Page 38

• Manufacturer Part Number: w65c134s
• Description: W65c134s 8-bit Microcontroller
• Manufacturer: Western Design Center, Inc.

2.15 Level Sensitive Interrupt Request inputs (IRQxB)
Port pins P41 and P42 I/O functions are multiplexed with IRQ1B and IRQ2B Level Sensitive Interrupt inputs
that are selected by Bus Control Register bit 6 (BCR6). When IRQxB is held low the associated Interrupt
Flag is set to a "1" in the Interrupt Flag Register Two (IFR2). When the associated Interrupt Enable Register
Two (IER2) bit is set to a "1" the MPU will be interrupted provided the I flag of the MPU is cleared to a "0"
allowing interrupts. Unlike the edge interrupts, which do not hold the interrupt bit set, an interrupt will be
generated as long as IRQxB is low.
2.16 Non-Maskable Edge Interrupt Input (NMIB)
Port pin P40 I/O function is multiplexed with NMIB edge triggered interrupt and is controlled by Bus Control
Register bit 6 (BCR6). When NMIB is selected by setting BCR6 equal to "1", the MPU will be interrupted on
all negative edges of NMIB. Since the I flag cannot prevent NMI- from interrupting, NMIB is thought of as
non-maskable, once enabled in the Bus Control Register.
2.17 Asynchronous Receive Input/Transmitter Output (RXD,TXD)
The W65C134S has a full duplex Universal Asynchronous Receiver and Transmitter (UART) that may be
enabled by the Asynchronous Control and Status Register (ACSR). When the Receiver is enabled by
ACSR5=1 then port pin P60 becomes the Asynchronous Receiver Input (RXD). When the Transmitter is
enabled by ACSR0=1, then port pin P61 becomes the Asynchronous Transmitter Output (TXD).
2.18 Timer A Input and Output (TIN, TOUT)
Timer A is controlled by TCR1x (see TCR1x for more information). When the UART is not in use, Timer A
can be used for counting input negative pulses on TIN. Timer A can also be used to put out a square wave
or rectangular wave form on TOUT. When counting negative pulses on TIN, the TIN frequency should
always be less than one-half the frequency of PHI2. TOUT changes state on every time-out of Timer A;
therefore, varying waveform and frequency depends on the timer latch values and may be modified under
software control.
2.19 The Serial Interface Bus (SIB) pins. (see Figure 1-13 Serial Interface Bus (SIB) Message Transmission
Timing diagram.)
2.19.1 CHIN Serial Interface Bus (SIB) CHain INput for token passing. CHIN (CHain INput) is
2.19.2 CHOUT SIB CHain OUTput for token passing.
2.19.3 SCLK Serial Clock for the SIB.
2.19.4 SDAT Serial Data for the SIB.
connected to CHOUT (CHain OUTput) of the previous device on the chain. When high it
indicates that this device can be master because all devices between the previous master
and this device are not master.
CHOUT goes to CHIN of the next device on the chain.
SCLK is connected to all devices. It is connected to the output of the serial clock generator in
the device in which the clock generator is enabled. It synchronously advances the state
machines for sending and receiving in all devices and also shifts data serially from the
sending device to a receiving device.
SDAT is connected to all devices. When it is not being driven during a data transfer, it should
be connected to an external current source to suppress noise transients. When a message
is not being sent, a device that wants to send a message pulls it low to start the serial clock
generator. When a message is being sent, the device that is sending uses it to convey data
to all other devices. At the end of the message the receiving device uses it to acknowledge
reception to the master.
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