w65c134s Western Design Center, Inc., w65c134s Datasheet - Page 20

• Manufacturer Part Number: w65c134s
• Description: W65c134s 8-bit Microcontroller
• Manufacturer: Western Design Center, Inc.

this means that the SIB was master before the last time mastery changed. One device is chosen as previous
master (one MPU on the network writes a "1" to SCSR2) before the first message is sent. SCSR2 is set to a "1"
for one SIB on the network as part of system initialization upon power up or reset. This bit is ignored during
normal system operation.
The SIB causes a SIBIRQ (SIB interrupt) when the SIB enable bit of the Bus Control Register is set
(BCR2=1) and SCSR1=1 (SIB master is set), or SCSR3=1 ISIB message not acknowledged), or SCSR4=1
(reading pending).
SCSR ($0019)
1.11.3.2
1.11.3.3
1.11.3.4
1.11.3.5
1.11.3.6
1.11.3.7
SIBIRQ
7
SCSR2 is the "previous master" control and status bit. When SCSR2 is set to a "1",
SCSR3 is the "message not acknowledged" status bit of SCSR. When
SCSR3 is set to a "1" by the SIB logic due to SDAT equals a "1" during
timing state 36, this means that the last message this SIB sent was not
acknowledged by the receiver whose address matches the Bus Address
Register (BAR) field of the message (SR35, SR36 and SR37).
SCSR4 is the "read pending" status bit of the SCSR. When SCSR4 is set
to a "1" due to a match between the incoming message BAR field with the
BAR, this means that the SIB has received a message but its processor
has not yet finished reading it. It is reset when SR3, the last byte of the
message, is read.
SCSR5 is the "deaf" status bit of the SIB. When SCSR5 is set to a "1" this
means that the SIB cannot receive a message in progress because when
the message started, its processor had not read its previous message.
SCSR6 is the "serial clock enable" control bit of SCSR. When SCSR6 is
set to a "1" by the on-chip MPU this means that the serial clock generator
(PHI2) in this device is enabled and provides the serial clock (SCLK) for the
system. SCSR6 is set to a "1" for one SIB on the network as part of system
initialization upon power up or reset. It is not used as part of the normal
communication sequence.
SCSR7 is the SIB interrupt flag bit that is set by a SIB interrupt condition
and reset to zero by a write of a "1" to SCSR7. A write of a "0" has no effect
on SCSR7.
SIBIRQ=BCR2 C (SCSR1+SCSR3+SCSR4)
SIB Serial Clock Enable
Figure 1-12 SIB Control and Status Register (SCSR)
6
SIB Deaf
5
SIB Read Pending
4
SIB Message Not Acknowledged
3
SIB Previous Master
2
SIB Master
1
SIB Write Pending
0
20