w65c134s Western Design Center, Inc., w65c134s Datasheet - Page 21

• Manufacturer Part Number: w65c134s
• Description: W65c134s 8-bit Microcontroller
• Manufacturer: Western Design Center, Inc.

1.11.4 Sequence of events for the SIB message transmission.
1.11.4.1
1.11.4.2
1.11.4.3
1.11.4.4
State 0 events (STATE=$01) The SIB controllers wait for some device to
request mastery. All devices on the serial bus wait for one or more devices
to request mastery. At any time any processor with data to send sets
SCSR0 (write pending) and the SIB is in state 0 (STATE=$01) then the
following occurs:
1. SCLK stops running.
2. Each device with SCSR0=1 pulls SDAT low to request SCLK.
3. SCLK restarts and advances the state machine to state 1
State 1 events (STATE=$02)
The SIB controllers establish mastery for this message. State 1 determines
which devices is master for this message and insures that SDAT is high on
transition to state 2 (STATE=$04) in state 1 (STATE=$02) the following
occurs:
1. The device that was master just before transition to state 1 sets SCSR2
2. The device with SCSR2 set to a "1" makes its CHOUT high. Other
3. The device that is master for this message outputs a high level on
4. SCLK advances to state 2 (STATE=$04).
State 2 events (STATE=$04)
The master's SIB controller waits for data from its processor. The SIB waits
in state 2 (STATE=$04) for the master to load its data and the following
occurs:
1. SCLK stops running.
2. The SIB controller that is master sets SCSR7 to interrupt and signal its
3. In response to the interrupt the processor should:
4. The master pulls SDAT low to request SCLK.
5. After at least one-half-cycle, SCLK advances the state counter to state 3
States 3 through 34 events (STATE=$08)
The message is sent. During state 3 through 34 (STATE=$08) the SIB
transfers the message from the master's shift register to all devices that
have read their previous messages.
(STATE=$02).
(previous master), and all other devices reset SCSR2.
devices only make CHOUT high if both their CHIN is high and
SCSR0=0. Thus the first device in the chain after the previous master
that has write pending (SCSR0=1) is the master for this message.
SDAT.
processor that it has acquired mastery.
a)
b)
c)
d)
(STATE=$08).
check "read pending" (SCSR4) to see if it has received a message
before acquiring mastery, and if so read it, thus clearing SCSR4;
check "message not acknowledged" SCSR3 to see if the last
message it sent was not acknowledged;
place the data it wants to send in SR0, SR1, SR2, and SR3, and;
clear "write pending" SCSR0 to signal the SIB controller that data is
there to send. This happens on the trailing edge of the write to SR0
so SR0 must be the last byte written into the shift register.
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