M25PX64-SOVME6F NUMONYX [Numonyx B.V], M25PX64-SOVME6F Datasheet
M25PX64-SOVME6F
Related parts for M25PX64-SOVME6F
M25PX64-SOVME6F Summary of contents
Page 1
... ECOPACK® (RoHS compliant) March 2008 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 64-Mbit, dual I/O, 4-Kbyte subsector erase, Rev 2 M25PX64 Preliminary Data VDFPN8 (ME) 8 × (MLP8) SO16 (MF) 300 mils width 1/66 www ...
Page 2
... Polling during a write, program or erase cycle . . . . . . . . . . . . . . . . . . . . . 13 4.5 Fast bulk erase mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.6 Active power, standby power and deep power-down modes . . . . . . . . . . 14 4.7 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.8 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.8.1 4.8.2 4.9 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.1 Write enable (WREN 6.2 Write disable (WRDI 2/66 Protocol-related protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Specific hardware and software protection . . . . . . . . . . . . . . . . . . . . . . 16 M25PX64 ) . . . . . . . . . . . . 10 PP ...
Page 3
... M25PX64 6.3 Read identification (RDID 6.4 Read status register (RDSR 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.5 Write status register (WRSR 6.6 Read data bytes (READ 6.7 Read data bytes at higher speed (FAST_READ 6.8 Dual output fast read (DOFR 6.9 Read lock register (RDLR 6.10 Read OTP (ROTP 6.11 Page program (PP 6.12 Dual input fast program (DIFP ...
Page 4
... DC characteristics Table 17. AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 18. VDFPN8 (MLP8) 8-lead very thin dual flat package no lead, 8 × 6 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 19. SO16 wide - 16-lead plastic small outline, 300 mils body width, mechanical data . . . . . . . 63 Table 20. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 21. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4/66 M25PX64 ...
Page 5
... M25PX64 List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. VDFPN8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. SO16 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 6. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 7. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 8. Write enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 9. Write disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 10 ...
Page 6
... Description 1 Description The M25PX64 is a 64-Mbit (8 Mbits x 8) serial flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The M25PX64 supports two new, high-performance dual input/output instructions: Dual output fast read (DOFR) instruction used to read data MHz by using ...
Page 7
... V CC DQ0 C M25PX64 S W/V PP HOLD V SS Function Serial Clock Serial Data input Serial Data output Chip Select Write Protect/Enhanced Program supply voltage Hold Supply voltage Ground M25PX64 DQ1 2 7 HOLD W DQ0 section for package dimensions, and how to identify pin-1. ...
Page 8
... Description Figure 3. SO16 connections don’t use. 2. See Package mechanical 8/66 M25PX64 HOLD DQ1 8 9 section for package dimensions, and how to identify pin-1. M25PX64 C DQ0 W/V PP AI13721c ...
Page 9
... M25PX64 2 Signal descriptions 2.1 Serial data output (DQ1) This output signal is used to transfer data serially out of the device. Data are shifted out on the falling edge of Serial Clock (C). During the dual input fast program (DIFP) instruction, pin DQ1 is used as an input latched on the rising edge of the Serial Clock (C). ...
Page 10
... the supply voltage. CC 2.8 V ground the reference for the V SS 10/66 Table 9). (as defined in Table 14) it acts as an additional power supply PPH must be stable until the bulk erase algorithm is PP supply voltage. CC M25PX64 ) PP ) the pin is seen as a control CC ...
Page 11
... Resistors R (represented in that the M25PX64 is not selected if the bus master leaves the S line in the high impedance state. As the bus master may enter a state where all inputs/outputs are in high impedance at ...
Page 12
... R*C p master never leaves the SPI bus in the high impedance state for a time period shorter than 5 µs. Figure 5. SPI modes supported CPOL CPHA DQ0 DQ1 12/ µs <=> the application must ensure that the bus p MSB M25PX64 MSB AI13730 ...
Page 13
... M25PX64 4 Operating features 4.1 Page programming To program one data byte, two instructions are required: write enable (WREN), which is one byte, and a page program (PP) sequence, which consists of four bytes plus data. This is followed by the internal program cycle (of duration t To spread this overhead, the page program (PP) instruction allows up to 256 bytes to be programmed at a time (changing bits from ‘ ...
Page 14
... V PP must be 25 °C ±10 ° Section 6.18: Deep power-down Section 6.4: Read status register (RDSR) (see Table 13) PPH should be less than 80 hours. PPH . The device CC2 (DP)), this can be used as an extra M25PX64 is PPH . CC1 for a ...
Page 15
... The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25PX64 features the following data protection mechanisms: Power on reset and an internal timer (t changes while the power supply is outside the operating specification ...
Page 16
... Sector protected from program/erase/write operations, protection status reversible Sector unprotected from program/erase/write operations, Sector protection status cannot be changed except by a power-up. Sector protected from program/erase/write operations, Sector protection status cannot be changed except by a power-up. bits) and the top/bottom bit (see M25PX64 Table 9: Lock register out. Section 6.4.4: ...
Page 17
... M25PX64 Table 3. Protected area sizes Status register contents bit bit 2 bit 1 bit none Upper 64th (2 sectors: 126 and 127 Upper 32nd (4 sectors: 124 to 127 Upper 16th (8 sectors: 120 to 127 Upper 8th (16 sectors 63) ...
Page 18
... To restart communication with the device necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents the device from going back to the hold condition. Figure 6. Hold condition activation C HOLD 18/66 Figure 6). Hold condition (standard use) M25PX64 Figure 6). Hold condition (non-standard use) AI02029D ...
Page 19
... M25PX64 5 Memory organization The memory is organized as: 8 388 608 bytes (8 bits each) 2048 subsectors (4 Kbytes each) 128 sectors (64 Kbytes each) 32768 pages (256 bytes each) 64 OTP bytes located outside the main memory array. Each page can be individually programmed (bits are programmed from ‘1’ to ‘0’). The device is subsector, sector or bulk erasable (bits are erased from ‘ ...
Page 20
... M25PX64 Subsector Address range 1871 74F000h 74FFFFh 1856 740000h 740FFFh 1855 73F000h 73FFFFh 1840 730000h 730FFFh 1839 72F000h 72FFFFh 1824 720000h ...
Page 21
... M25PX64 Table 4. Memory organization (continued) Sector Subsector 1695 105 1680 1679 104 1664 1663 103 1648 1647 102 1632 1631 101 1616 1615 100 1600 1599 99 1584 1583 98 1568 1567 97 1552 1551 96 1536 1535 95 1520 Address range Sector 69F000h 69FFFFh 94 690000h ...
Page 22
... M25PX64 Subsector Address range 1167 48F000h 48FFFFh 1152 480000h 480FFFh 1151 47F000h 47FFFFh 1136 470000h 470FFFh 1135 46F000h 46FFFFh 1120 460000h 460FFFh 1119 ...
Page 23
... M25PX64 Table 4. Memory organization (continued) Sector Subsector 991 61 976 975 60 960 959 59 944 943 58 928 927 57 912 911 56 896 895 55 880 879 54 864 863 53 848 847 52 832 831 51 816 Address range Sector 3DF000h 3DFFFFh 50 3D0000h 3D0FFFh 3CF000h 3CFFFFh 49 3C0000h 3C0FFFh 3BF000h ...
Page 24
... M25PX64 Subsector Address range 463 1CF000h 1CFFFFh 448 1C0000h 1C0FFFh 447 1BF000h 1BFFFFh 432 1B0000h 1B0FFFh 431 1AF000h 1AFFFFh 416 1A0000h 1A0FFFh 415 ...
Page 25
... M25PX64 Table 4. Memory organization (continued) Sector Subsector 287 17 272 271 16 256 255 15 240 239 14 224 223 13 208 207 12 192 191 11 176 175 10 160 159 9 144 143 8 128 Address range Sector 11F000h 11FFFFh 7 110000h 110FFFh 10F000h 10FFFFh 6 100000h 100FFFh FF000h FFFFFh 5 F0000h ...
Page 26
... All attempts to access the memory array during a write status register cycle, program cycle or erase cycle are ignored, and the internal write status register cycle, program cycle or erase cycle continues unaffected. Note: Output Hi-Z is defined as the point where data out is no longer driven. 26/66 Table 5. M25PX64 ...
Page 27
... M25PX64 Table 5. Instruction set Instruction Description WREN Write enable WRDI Write disable RDID Read identification RDSR Read status register WRSR Write status register WRLR Write to lock register RDLR Read lock register READ Read data bytes FAST_READ Read data bytes at higher speed ...
Page 28
... The write enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. Figure 8. Write enable (WREN) instruction sequence 28/66 (Figure 8) sets the write enable latch (WEL) bit Instruction DQ0 High Impedance DQ1 AI13731 M25PX64 ...
Page 29
... M25PX64 6.2 Write disable (WRDI) The write disable (WRDI) instruction The write disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. The write enable latch (WEL) bit is reset under the following conditions: Power-up ...
Page 30
... Table 6. Read identification (RDID) data-out sequence Manufacturer identification 20h 30/66 Figure 10. Device identification Memory type Memory capacity 71h 17h M25PX64 UID CFD length CFD content 10h 16 bytes ...
Page 31
... M25PX64 Figure 10. Read identification (RDID) instruction sequence and data-out sequence Instructions 31/66 ...
Page 32
... BP1, BP0) bits can be written provided that the hardware protected mode has not been set. The bulk erase (BE) instruction is executed if, and only if, all block protect (BP2, BP1, BP0) bits are 0. 32/ BP2 Top/bottom bit Block protect bits M25PX64 Figure 11. BP1 BP0 WEL Write enable latch bit Write in progress bit Table ...
Page 33
... M25PX64 6.4.4 Top/bottom bit The top/bottom (TB) bit is non-volatile. It can be set and reset with the write status register (WRSR) instruction provided that the write enable (WREN) instruction has been issued. The top/bottom (TB) bit is used in conjunction with the block protect (BP0, BP1, BP2) bits to ...
Page 34
... The write status register (WRSR) instruction also allows the ) signal. The status register write disable (SRWD) bit and Write Protect Instruction 7 High Impedance MSB Status register AI13735 M25PX64 ) is initiated. ...
Page 35
... M25PX64 Table 8. Protection modes W/V SRWD PP signal bit defined by the values in the block protect (BP2, BP1, BP0) bits of the status register, as shown in Table 3. The protection features of the device are summarized in When the status register write disable (SRWD) bit of the status register is 0 (its initial ...
Page 36
... DQ0 DQ1 1. Address bit A23 is don’t care. 36/66 Figure 13 Instruction 24-bit address MSB High Impedance ( Data out MSB M25PX64 39 Data out AI13736b ...
Page 37
... M25PX64 6.7 Read data bytes at higher speed (FAST_READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the read data bytes at higher speed (FAST_READ) instruction is followed by a 3-byte address (A23- A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). ...
Page 38
... High Impedance Dummy byte DATA OUT 1 DATA OUT 2 DATA OUT MSB MSB M25PX64 ( DATA OUT ...
Page 39
... M25PX64 6.9 Read lock register (RDLR) The device is first selected by driving Chip Select (S) Low. The instruction code for the read lock register (RDLR) instruction is followed by a 3-byte address (A23-A0) pointing to any location inside the concerned sector. Each address bit is latched-in during the rising edge of Serial Clock (C) ...
Page 40
... Instruction 24-bit address High Impedance Dummy byte DATA OUT MSB DATA OUT MSB M25PX64 0 7 MSB AI13573 ...
Page 41
... M25PX64 6.11 Page program (PP) The page program (PP) instruction allows bytes to be programmed in the memory (changing bits from ‘1’ to ‘0’). Before it can be accepted, a write enable (WREN) instruction must previously have been executed. After the write enable (WREN) instruction has been decoded, the device sets the write enable latch (WEL). ...
Page 42
... MSB Data byte MSB Data byte 1 ( MSB Data byte 256 MSB M25PX64 AI13739b ...
Page 43
... M25PX64 6.12 Dual input fast program (DIFP) The dual input fast program (DIFP) instruction is very similar to the page program (PP) instruction, except that the data are entered on two pins (pin DQ0 and pin DQ1) instead of only one. Inputting the data on two pins instead of one doubles the data transfer bandwidth compared to the page program (PP) instruction ...
Page 44
... DATA IN 2 DATA MSB MSB MSB ( DATA IN 4 DATA IN 5 DATA IN 256 MSB MSB M25PX64 AI14229b ...
Page 45
... M25PX64 6.13 Program OTP instruction (POTP) The program OTP instruction (POTP) is used to program at most 64 bytes to the OTP memory area (by changing bits from ‘1’ to ‘0’, only). Before it can be accepted, a write enable (WREN) instruction must previously have been executed. After the write enable (WREN) instruction has been decoded, the device sets the write enable latch (WEL) bit ...
Page 46
... Data byte MSB Data byte MSB OTP control byte Byte Byte bit 0 When bit the 64 OTP bytes become read only ai13587 M25PX64 AI13575 ...
Page 47
... M25PX64 6.14 Write to lock register (WRLR) The write to lock register (WRLR) instruction allows bits to be changed in the lock registers. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. After the write enable (WREN) instruction has been decoded, the device sets the write enable latch (WEL) ...
Page 48
... Figure 23. Subsector erase (SSE) instruction sequence S C DQ0 1. Address bit A23 is don’t care. 48/66 Table valid address for the subsector erase (SSE) instruction. Figure 23 Instruction 23 22 MSB 24-bit address ( AI13741b M25PX64 ) is SSE ...
Page 49
... M25PX64 6.16 Sector erase (SE) The sector erase (SE) instruction sets to ‘1’ (FFh) all bits inside the chosen sector. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. After the write enable (WREN) instruction has been decoded, the device sets the write enable latch (WEL) ...
Page 50
... The bulk erase (BE) instruction is executed only if all block protect (BP2, BP1, BP0) bits are 0. The bulk erase (BE) instruction is ignored if one, or more, sectors are protected. Figure 25. Bulk erase (BE) instruction sequence 50/66 Figure 25 Instruction DQ0 ) is initiated. While the AI13743 M25PX64 ...
Page 51
... M25PX64 6.18 Deep power-down (DP) Executing the deep power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the deep power-down mode). It can also be used as a software protection mechanism, while the device is not in active use this mode, the device ignores all write, program and erase instructions. ...
Page 52
... Figure 27. Release from deep power-down (RDP) instruction sequence S C DQ0 DQ1 52/66 Figure 27 Instruction High Impedance Deep power-down mode M25PX64 , the device is put in the RDP t RDP Standby mode AI13745 ...
Page 53
... M25PX64 7 Power-up and power-down At power-up and power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied (min) at power-up, and then for a further delay power-down safe configuration is provided in To avoid data corruption and inadvertent write operations during power-up, a power on reset (POR) circuit is included ...
Page 54
... FFh). The status register contains 00h (all status register bits are 0). 54/66 Program, erase and write commands are rejected by the device Chip selection not allowed tVSL tPUW threshold WI Parameter M25PX64 Read access allowed Device fully accessible time AI04009C Min Max Unit ...
Page 55
... M25PX64 9 Maximum ratings Stressing the device outside the ratings listed in cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...
Page 56
... Input capacitance (other pins Sampled only, not 100% tested 56/66 Parameter pin for fast bulk erase mode PP Parameter Input levels timing reference levels 0.8V CC 0.2V CC (1) Parameter Test condition V =25 °C and a frequency of 33 MHz. A M25PX64 Min Typ Max 2.7 3.6 8.5 9.5 – Min Max ...
Page 57
... M25PX64 Table 16. DC characteristics Symbol I Input leakage current LI I Output leakage current LO I Standby current CC1 I Deep Power-down current CC2 Operating current (READ) I CC3 Operating current (DOFR) Operating current (PP) I CC4 Operating current (DIFP) I Operating current (WRSR) CC5 I Operating current (SE) ...
Page 58
... Chip Select Low PPH S High to deep power-down mode S High to standby mode Table 13 and Table 14 (2) Min Typ D.C. D. 0.1 0 100 200 M25PX64 Max Unit 75 MHz 33 MHz ns ns V/ns V/ ...
Page 59
... M25PX64 Table 17. AC characteristics Symbol Alt ( SSE Preliminary data. 2. Typical values given for must be greater than or equal Value guaranteed by characterization, not 100% tested in production. 5. Expressed as a slew-rate. 6. Only applicable as a constraint for a WRSR instruction when SRWD is set to ‘1’. ...
Page 60
... DC and AC parameters Figure 31. Write protect setup and hold timing during WRSR when SRWD=1 W/V PP tWHSL S C DQ0 DQ1 Figure 32. Hold timing S C DQ1 DQ0 HOLD 60/66 High Impedance tHLCH tCHHL tCHHH tHLQZ M25PX64 tSHWL AI07439c tHHCH tHHQX AI13746 ...
Page 61
... M25PX64 Figure 33. Output timing S C tCLQV tCLQX DQ1 ADDR. DQ0 LSB IN Figure 34. V PPH S C DQ0 V PPH V PP tCLQV tCLQX timing BE tVPPHSL DC and AC parameters tCH tCL LSB OUT tQLQH tQHQL End of BE (identified by WIP polling) tSHQZ AI13729 ai13726 61/66 ...
Page 62
... D2 Max must not exceed (D – K – 2 × L). 62/ Millimeters Typ Min Max 0.85 1.00 0.00 0.05 0.40 0.35 0.48 8.00 (1) 5.16 0.05 6.00 4.80 1.27 – – 0.82 0.50 0.45 0.60 0. ddd VDFPN-02 Inches Typ Min 0.033 0.000 0.016 0.014 0.315 0.203 0.236 0.189 0.050 – 0.032 0.020 0.018 8 M25PX64 Max 0.039 0.002 0.019 0.002 – 0.024 0.006 ...
Page 63
... M25PX64 Figure 36. SO16 wide - 16-lead plastic small outline, 300 mils body width, package outline SO-H 1. Drawing is not to scale. Table 19. SO16 wide - 16-lead plastic small outline, 300 mils body width, mechanical data Symbol θ ddd ...
Page 64
... F = tape and reel packing ECOPACK® (RoHS compliant) 1. Secure options are available upon customer request. Note: For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest Numonyx sales office. 64/66 (1) M25PX64 M25PX64 – ...
Page 65
... M25PX64 13 Revision history Table 21. Document revision history Date Revision 05-Nov-2007 25-Mar-2008 1 Initial release. Updated the minimum value for t 2 Applied Numonyx branding. Revision history Changes in Table 17: AC characteristics. SHSL 65/66 ...
Page 66
... Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. 66/66 Please Read Carefully: applications. visiting Numonyx's website at http://www.numonyx.com. Copyright © 11/5/7, Numonyx B.V. All Rights Reserved. M25PX64 ...