PF38F5070M0Y0T0 NUMONYX [Numonyx B.V], PF38F5070M0Y0T0 Datasheet
PF38F5070M0Y0T0
Related parts for PF38F5070M0Y0T0
PF38F5070M0Y0T0 Summary of contents
Page 1
Numonyx™ StrataFlash (L18) with AD-Multiplexed I/O Product Features High performance Read-While-Write/Erase — initial access — 54MHz with zero wait state clock-to- data output synchronous-burst mode — 4-, 8-, 16-, and continuous-word burst mode — Burst suspend ...
Page 2
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE ...
Page 3
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) Contents 1.0 Introduction .............................................................................................................. 7 1.1 Nomenclature ..................................................................................................... 7 1.2 Acronyms........................................................................................................... 7 1.3 Conventions ....................................................................................................... 8 2.0 Functional Overview .................................................................................................. 9 3.0 Package Information ............................................................................................... 10 4.0 Ballout and Signal Descriptions ............................................................................... 12 ...
Page 4
WAIT Delay............................................................................................46 10.3.6 Burst Sequence ......................................................................................47 10.3.7 Clock Edge.............................................................................................47 10.3.8 Burst Wrap ............................................................................................48 10.3.9 Burst Length ..........................................................................................48 11.0 Programming Operations .........................................................................................49 11.1 Word Programming ............................................................................................49 11.1.1 Factory Word Programming......................................................................50 11.2 Buffered Programming .......................................................................................50 11.3 Buffered Enhanced Factory Programming ..............................................................51 ...
Page 5
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) B.1 Common Flash Interface (CFI) ............................................................................ 83 B.2 Query Structure Output...................................................................................... 84 B.3 Query Structure Overview .................................................................................. 84 B.4 CFI Query Identification String ............................................................................ 85 B.5 Device Geometry Definition ................................................................................ 87 B.6 Intel-Specific ...
Page 6
Revision History Date Revision Description May 2006 001 Initial Release July 2006 002 Removed Intel Confidential status. August 2007 003 Updated ordering information November 2007 04 Applied Numonyx branding. Datasheet 6 ® Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) November 2007 ...
Page 7
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) 1.0 Introduction This document provides information about the Numonyx™ StrataFlash Memory (L18) with AD-Multiplexed I/O device. This document describes device features, operation, and specifications. The Numonyx™ StrataFlash is the latest generation of Intel ...
Page 8
RCR SR WSM 1.3 Conventions VCC Signal or voltage connection V Signal or voltage level CC 0x Hexadecimal number prefix 0b Binary number prefix SR[4] Denotes an individual register bit A[15:0] Denotes a group of similarly named signals, such as ...
Page 9
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) 2.0 Functional Overview The Numonyx™ StrataFlash provides read-while-write and read-while-erase capability with density upgrades through 256-Mbit. This device provides high performance at low voltage on a 16-bit data bus. Individually erasable memory blocks ...
Page 10
Package Information Figure 1: 64- and 128-Mbit, 88-ball (80-active ball) (8x10x1.2 mm ...
Page 11
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) Figure 2: 256-Mbit, 88-ball (80-active ball) (8x11x1.0 mm ...
Page 12
Ballout and Signal Descriptions Table 1: QUAD+ Ballout Pin A18 C A5 R-LB# A3 A17 DQ8 H R-OE# DQ0 J S-CS1# F1-OE# K ...
Page 13
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) 4.1 Signal Descriptions Table 2: Signal Descriptions (Sheet Symbol Type Address and Data Signals, AD-Mux ADDRESS: Global device signals. Shared address inputs for all memory die during Read and Write ...
Page 14
Table 2: Signal Descriptions (Sheet Symbol Type WAIT: Flash -and Synchronous PSRAM-specific signal; configurable true-level output. When asserted, WAIT indicates invalid output data. When deasserted, WAIT indicates valid output data. WAIT Output • WAIT is driven whenever ...
Page 15
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) Table 2: Signal Descriptions (Sheet Symbol Type DEVICE GROUND: Global ground reference for all signals and power supplies. Groun VSS d Connect all VSS balls to system ground. Do not ...
Page 16
Table 3: Top Parameter Memory Map, 128-Mbit (Sheet Size (KW) Blk Table 4: Top Parameter Memory Map, 256-Mbit Size (KW) Datasheet 16 Numonyx™ StrataFlash 64-Mbit 370000-37FFFF 000000-00FFFF Blk 16 258 16 257 ...
Page 17
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) 5.0 Maximum Ratings and Operating Conditions 5.1 Absolute Maximum Ratings Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Table 5: Absolute Maximum Ratings ...
Page 18
Electrical Specifications 6.1 DC Current Characteristics Table 7: DC Current Characteristics (Sheet Sym Parameter I Input Load Current LI Output I Leakage AD[15:0], LO WAIT Current I V Standby, CCS CC I Power Down CCD I ...
Page 19
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) Table 7: DC Current Characteristics (Sheet Sym Parameter I V Read PPR Program Current PPW Erase Current PPE PP Notes: 1. All currents are ...
Page 20
AC Characteristics 7.1 AC Test Conditions Figure 3: AC Input/Output Reference Waveform V CCQ Input V /2 CCQ 0V Note: AC test inputs are driven at V CCQ rise and fall times (10% to 90%) < 5 ns. Worst ...
Page 21
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) 7.2 Capacitance Table 10: Capacitance Symbol Parameter Address, CE#, WE#, C Input Capacitance OE#, RST#, CLK, IN ADV#, WP# C Output Capacitance Data, WAIT OUT Notes: 1. Sampled, not 100% tested. 2. Silicon ...
Page 22
Table 11: AC Read Specifications (V Num Symbol R200 f CLK frequency CLK R201 t CLK period CLK R202 t CLK high/low time CH/CL R203 t CLK fall/rise time FCLK/RCLK Synchronous Specifications R301 t Address setup to CLK AVCH/L R302 ...
Page 23
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) Table 12: AC Read Specifications (V Num Symbol R101 t Address setup to ADV# high AVVH R102 t CE# low to ADV# high ELVH R103 t ADV# low to output valid VLQV R104 ...
Page 24
Table 13: AC Read Specifications (Sheet Num Symbol Parameter R1 t Read cycle time AVAV t R2 Address to output valid AVQV R3 t CE# low to output valid ELQV R4 t OE# low to output valid ...
Page 25
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) Table 13: AC Read Specifications (Sheet Num Symbol Parameter R305 t Output hold from CLK CHQX R306 t Address hold from CLK CHAX R307 t CLK to WAIT valid CHTV ...
Page 26
Figure 7: Synchronous Array Read with Flow-through Feature Timing First Acces s Latency CLK [C] A[m ax:16] [ A/DQ[15:0] A R106 R102 ADV# [V] R303 CE# [E] R107 OE# [G] R12 R15 WAIT [T] Notes: 1. WAIT active ...
Page 27
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) Figure 9: Burst Suspend Timing Latenc CLK [C] ADQ [ADQ] A R101 R105 R105 R106 ADV# [V] CE# [E] R107 OE# [G] R12 WAIT [T] WE# [W] Notes: 1. During burst suspend Clock ...
Page 28
Figure 11: Write to Asynchronous Read Timing A[Max:16][ A/DQ [15: R106 R101 R104 R104 ADV#[V] W2 CE# [ WE# [W] OE# [G] R12 WAIT [T] W1 RST#[P] Note: WAIT deasserted (CR[10] = ...
Page 29
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) Figure 12: Synchronous Read to Write Timing R306 CLK R301 R2 A[Max:16] [ A/DQ[15:0] A R106 R104 R104 R101 ADV# [V] CE# [E] R4 OE# [G] R12 R15 WAIT [T] ...
Page 30
Figure 13: Write to Synchronous Read CLK [C] A[Max:16] [ A/DQ[15: R106 R104 R104 R101 ADV# [V] W2 CE# [ WE# OE# [G] R12 WAIT [T] Note: WAIT shown deasserted (CR[10 during ...
Page 31
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) Table 14: AC Write Specifications (Sheet Num Symbol W15 t ADV# low to WE# high VLWH W16 t WE# high to read valid WHQV Write to Asynchronous Read Specification W18 ...
Page 32
Program and Erase Characteristics Table 15: Program and Erase Characteristics Num Symbol Program W200 t PROG/W Time W200 t PROG/W Program Time W201 t PROG/PB W400 t BEFP/W Program t BEFP/ W452 SETUP W500 t ERS/PB Erase Time W501 ...
Page 33
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) 8.0 Power and Reset Specifications 8.1 Power Up and Down Power supply sequencing is not required if VCC, VCCQ, and VPP are connected together. If VCCQ and/or VPP are not connected to the ...
Page 34
Figure 15: Reset Operation Waveforms (A) Reset during read mode (B) Reset during program or block erase P1 ≤ P2 (C) Reset during program or block erase P1 ≥ P2 (D) VCC Power-up to RST# high Table 16: Reset Specifications ...
Page 35
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) When the device is accessed, many internal conditions change. Circuits within the device enable charge-pumps, and internal logic states change at high speed. All of these internal activities produce transient signals. Transient current ...
Page 36
Device Operations This section provides an overview of device operations. The system CPU provides control of all in-system read, write, and erase operations of the device via the system bus. The on-chip Write State Machine (WSM) manages all block-erase ...
Page 37
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) 9.1.4 Standby When CE# is deasserted the device is deselected and placed in standby, substantially reducing power consumption. In standby, the data outputs are placed in High-Z, independent of the level placed on ...
Page 38
Table 17: Command Bus Cycles Mode Command Read Array Read Device Identifier Read CFI Query Read Status Register Clear Status Register Word Program Program Buffered Program Buffered Enhanced Factory Program (Buffered EFP) Erase Block Erase Program/Erase Suspend Suspend Program/Erase Resume ...
Page 39
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) Table 18: Command Codes and Definitions (Sheet Mode Code Device Mode 0xFF Read Array Read Status 0x70 Register Read Device ID Read 0x90 or Configuration Register 0x98 Read Query Clear ...
Page 40
Table 18: Command Codes and Definitions (Sheet Mode Code Device Mode 0x60 Lock Block Setup 0x01 Lock Block Block Locking/ Unlocking 0xD0 Unlock Block 0x2F Lock-Down Block Program Protection 0xC0 Protection Register Setup Configure Read 0x60 Configuration ...
Page 41
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) 10.0 Read Operations The device supports two read modes: asynchronous read mode and synchronous burst mode. Asynchronous array read mode is the default read mode after device power- reset. The Read ...
Page 42
All subsequent data is driven on valid clock edges following the first access latency; however, for a synchronous non-array read, the same word of data ...
Page 43
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) Table 19: Read Configuration Register Description (Sheet 13:11 Latency Count (LC[2:0]) 10 Wait Polarity (WP) 9 Data Hold (DH) 8 Wait Delay (WD) 7 Burst Sequence (BS) 6 Clock Edge ...
Page 44
Figure 16: First-Access Latency Count CLK Valid Address Address ADV# Code 2 AD[15:0] Code 3 AD[15:0] Code 4 AD[15:0] Code 5 AD[15:0] Code 6 AD[15:0] Code 7 AD[15:0] Table 20: LC and Frequency Support (t Latency Count Settings 2 3 ...
Page 45
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) Figure 17: Example Latency Count Setting with Flow- through feature t ADD CLK CE# ADV# A MAX-16 Code 4 A/DQ Valid Address 15-0 Note: The waveform above illustrates the Latency Count of 4 ...
Page 46
Note: Active: WAIT is asserted until data becomes valid, then de-asserts. WAIT is asserted during the initial access (latency) and at the end of the burst cycle with OE# low. 10.3.4 Data Hold For burst read operations, the Data Hold ...
Page 47
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) 10.3.6 Burst Sequence The Burst Sequence (BS) bit selects linear-burst sequence (default). Only linear-burst sequence is supported. lengths, as well as the effect of the Burst Wrap (BW) setting. Table 23: Burst Sequence ...
Page 48
Burst Wrap The Burst Wrap (BW) bit determines whether 4-word, 8-word, or 16-word burst length accesses wrap within the selected word-length boundaries or cross over to the next burst-length segment. When BW is set, burst wrapping does not occur ...
Page 49
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) 11.0 Programming Operations The device supports three programming methods: word programming, buffered programming, and Buffered Enhanced Factory Programming (Buffered EFP). See Section 9.0, “Device Operations” on page 36 commands issued to the device. ...
Page 50
Factory Word Programming Factory word programming is similar to word programming in that it uses the same commands and programming algorithms. However, factory word programming enhances the programming performance with V programming times during OEM manufacturing processes. Factory word ...
Page 51
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux attempt is made to program past an erase-block boundary using the Buffered Program command, the device aborts the operation. This generates a command sequence error, and Status Register bits SR[5,4] are ...
Page 52
Read operation while performing Buffered EFP is not supported. Notes: 1. Word buffer boundaries in the array are determined by A[4:0] (0x00 through 0x1F). The alignment start point is A[4:0] = 0x00. 2. Some degradation in performance may occur ...
Page 53
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) 11.3.4 Buffered EFP Exit Phase When SR[7] is set, the device has returned to normal operating conditions. A full status check should be performed at this time to ensure the entire block programmed ...
Page 54
Figure 19: Example VPP Supply Connections ≤ 10K Ω • Factory Programming with • Complete write/Erase Protection when PPH • Low Voltage and Factory Programming Datasheet 54 Numonyx™ StrataFlash V VCC ...
Page 55
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) 12.0 Erase Operations Flash erasing is performed on a block basis. An entire block is erased each time an erase command sequence is issued, and only one block is erased at a time. ...
Page 56
To read data from blocks within the suspended partition (other than an erase- suspended block), the Read Array command must be issued to that partition first. During Erase Suspend, a Program command can be issued to any block other than ...
Page 57
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) 13.0 Security Modes The device features security modes used to protect the information stored in the flash memory array. The following sections describe each security mode in detail. 13.1 Block Locking Individual instant ...
Page 58
A locked-down block can only be unlocked by issuing the Unlock Block command with WP# deasserted. To return an unlocked block to locked-down state, a Lock command (60h/01h) must be issued prior to changing WP unlocked block ...
Page 59
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) Note: A Lock Block Setup command followed by any command other than Lock Block, Unlock Block, or Lock-Down Block produces a command sequence error and set Status Register bits SR[4] and SR[5]. If ...
Page 60
Figure 21: Protection Register Map 0x109 0x102 0x91 0x8A 0x89 0x88 0x85 0x84 0x81 0x80 . 13.2.1 Reading the Protection Registers The Protection Registers can be read from within any partition’s address space. To read the Protection Register, first issue ...
Page 61
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) 13.2.2 Programming the Protection Registers To program any of the Protection Registers, first issue the Program Protection Register command at the parameter partition’s base address plus the offset to the desired Protection Register ...
Page 62
Dual-Operation Considerations The multi-partition architecture of the device allows background programming (or erasing) to occur in one partition while data reads (or code execution) take place in another partition. 14.1 Memory Partitioning The flash memory array is divided into ...
Page 63
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) Figure 23: Operating Mode with Correct Command Sequence Example Addr/Data [A/D] Partition A ADV# CE# WE# [W] OE# [G] Figure 24: Operating Mode with Illegal Command Sequence Example Addr/Data [A/D] Part. A Data: ...
Page 64
Write Operation with Clock Active W21 - t VHWL W22 - t CHWL The AC parameters W21 (t to WE# low) are required when the device synchronous mode and clock is active. A write bus cycle ...
Page 65
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) Table 25: Simultaneous Operation Restrictions Protection Parameter Other Register or Partition Partitions CFI data Array Data Read (See Notes) Write/Erase (See Notes) Read Write/Erase Read Read Write/Erase No Access Write Allowed No Access ...
Page 66
Special Read States The following sections describe non-array read states. Non-array reads can be performed in asynchronous read or synchronous burst mode. A non-array read operation is exactly the same as an array read. However, when using synchronous burst ...
Page 67
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) Table 26: Status Register Description (Sheet Status Register (SR) Program Suspend Status 2 (PSS) 1 Block-Locked Status (BLS) 0 Partition Write Status (PWS) Always clear the Status Register prior to ...
Page 68
Table 27: Device Identifier Information (Sheet Item Lock Register 0 64-bit Factory-Programmed Protection Register 64-bit User-Programmable Protection Register Lock Register 1 128-bit User-Programmable Protection Registers Notes: 1. PBA = Partition Base Address. 2. BBA = Block Base ...
Page 69
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) Appendix A Write State Machine Figure 25 through based on incoming commands. Only one partition can be actively programming or erasing at a time. Each partition stays in its last read state (Read ...
Page 70
Figure 26: Write State Machine—Next State Table (Sheet Read Word Current Chip (2) (3,4) Array Program (7) State (FFH) (10H/40H) Setup Word Program Busy in Erase Suspend Busy Word Program in Erase Suspend Word Program Suspend in ...
Page 71
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) Figure 27: Write State Machine—Next State Table (Sheet Command Input to Chip and resulting Chip Next State Lock OTP Block Current Chip (4) Setup (8) Confirm (7) State (C0H) (01H) ...
Page 72
Figure 28: Write State Machine—Next State Table (Sheet Command Input to Chip and resulting Chip Next State Lock OTP Block Current Chip (4) Setup (8) Confirm (7) State (C0H) (01H) Setup Busy Word Program Busy in Erase ...
Page 73
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) Figure 29: Write State Machine—Next State Table (Sheet Output Next State Table Word Read Program (2) Array Current chip state Setup (3,4) (FFH) (10H/40H) BEFP Setup, BEFP Pgm & Verify ...
Page 74
Figure 30: Write State Machine—Next State Table (Sheet Output Next State Table Command Input to Chip and resulting Output Mux Next State Lock OTP Block (4) Setup Current chip state Confirm (C0H) (01H) BEFP Setup, BEFP Pgm ...
Page 75
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) 6. BEFP writes are only allowed when the status register bit # else the data is ignored. 7. The "current state" is that of the "chip" and not of the ...
Page 76
Appendix B Flowcharts Figure 31: Word Program Flowchart Start Write 0x40, (Setup) Word Address Write Data, (Confirm) Word Address Read Status Register 0 SR[7] = Suspend? 1 Full Status Check (if desired) Program Complete Read Status Register V Range 1 ...
Page 77
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) Figure 32: Program Suspend/Resume Flowchart Start Program Suspend Write B0h Any Address Read Status Write 70h Same Partition Read Status Register Read Array Write FFh ...
Page 78
Figure 33: Buffer Program Flowchart Start Device Supports Buffer Writes? Yes Set Timeout or Loop Counter Get Next Target Address Issue Buffer Prog. Cmd. 0xE8, Word Address Read Status Register at Word Address Write Buffer Available? SR[7] ...
Page 79
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) Figure 34: Buffered EFP Flowchart BUFFERED ENHANCED FACTORY PROGRAMMING (Buffered-EFP) PROCEDURE Setup Phase Start V applied, PP Block unlocked Write 0x80 @ 1 ST Word Address Write 0xD0 @ 1 ST Word Address ...
Page 80
Figure 35: Block Erase Flowchart Start Write 0x20, (Block Erase) Block Address Write 0xD0, (Erase Confirm) Block Address Read Status Register Suspend 0 SR[7] = Erase 1 Full Erase Status Check (if desired) Block Erase Complete FULL ERASE STATUS CHECK ...
Page 81
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) Figure 36: Erase Suspend/Resume Flowchart Start Write 0x70, Same Partition Write 0xB0, Any Address Read Status Register SR[ SR[ Read Read or Program? Read Array No Data Done Write ...
Page 82
Figure 37: Block Lock Operations Flowchart Start Write 0x60, (Lock Setup) Block Address Write either 0x01/0xD0/0x2F, (Lock Confirm) Block Address Write 0x90 (Read Device ID) Read Block Lock Status Locking No Change? Yes Write 0xFF (Read Array) Partition Address Lock ...
Page 83
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) Figure 38: Protection Register Programming Flowchart PROTECTION REGISTER PROGRAMMING PROCEDURE Start Write 0xC0, (Program Setup) PR Address Write PR (Confirm Data) Address & Data Read Status Register 0 SR[ Full Status ...
Page 84
The system software will then know which command set(s) to use to properly perform flash writes, block erases, reads and otherwise ...
Page 85
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) Table 31: Query Structure Offset 00001-Fh Reserved 00010h CFI query identification string 0001Bh System interface information 00027h Device geometry definition (3) Primary Intel-specific Extended Query Table Vendor-defined additional information specific P Notes: 1. ...
Page 86
Table 33: System Interface Information Offset Length 1Bh 1 1Ch 1 1Dh 1 1Eh 1 1Fh 1 20h 1 21h 1 22h 1 23h 1 24h 1 25h 1 26h 1 Datasheet 86 Numonyx™ StrataFlash Description V logic supply minimum ...
Page 87
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) B.5 Device Geometry Definition Table 34: Device Geometry Definition Offset Length 1 27h 28h 2 2 2Ah 2Ch 1 4 2Dh 4 31h 35h 4 Address 27: 28: 29: 2A: 2B: 2C: 2D: ...
Page 88
B.6 Intel-Specific Extended Query Table Table 35: Primary Vendor-Specific Extended Query (1) Length Offset P= 10Ah (P+0)h 3 (P+1)h (P+2)h (P+3)h 1 (P+4)h 1 (P+5)h 4 (P+6)h (P+7)h (P+8)h (P+9)h 1 (P+A)h 2 (P+B)h (P+C)h 1 (P+D)h 1 Datasheet 88 ...
Page 89
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) Table 36: Protection Register Information (1) Length Offset P= 10Ah (P+E)h 1 (P+F)h 4 (P+10)h (P+11)h (P+12)h (P+13)h 10 (P+14)h (P+15)h (P+16)h (P+17)h (P+18)h (P+19)h (P+1A)h (P+1B)h (P+1C)h November 2007 Order Number: 313295-04 ...
Page 90
Table 37: Burst Read Information (1) Length Offset P= 10Ah (P+1D)h 1 (P+1E)h 1 (P+1F)h 1 (P+20)h 1 (P+21)h 1 (P+22)h 1 Table 38: Partition and Erase-block Region Information (1) Offset P= 10Ah Bottom Top (P+23)h (P+23)h Datasheet 90 Numonyx™ ...
Page 91
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) Table 39: Partition Region 1 Information (1) Offset P= 10Ah Bottom Top (P+24)h Number of identical partitions within the partition region (P+24)h (P+25)h (P+25)h (P+26)h (P+26)h Number of program or erase operations allowed ...
Page 92
Table 40: Partition Region 2 Information (1) Offset P= 10Ah Bottom Top (P+3A)h (P+32)h Number of identical partitions within the partition region (P+3B)h (P+33)h (P+3C)h (P+34)h Number of program or erase operations allowed in a partition bits 0–3 = number ...
Page 93
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) Table 41: Partition and Erase Block Information Address 64 M bit –B 12D : --02 12E: --01 12F: --00 130: --11 131: --00 132: --00 133: --02 134: --03 135: --00 136: --80 ...
Page 94
Table 42: Electrical Traceability 76h 76h (P+48)h (P+48)h Table 43: CFI Revision History for Engineering Sample at Address 76h Density CFI Field Data 000 0001 1100 OMPU 64 Mbit - Bin 1 OMPU 64 Mbit - Bin ...
Page 95
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) Table 44: CFI Revision History for Production Materials at Address 76h Density CFI Field Data 000 0001 0001 OMPU 64 Mbit - Bin 1 OMPU 64 Mbit - Bin 1 ...
Page 96
... Appendix C Ordering Information To order samples, obtain datasheets or inquire about any stack combination, please contact your local Intel representative. Table 45: 38F Type Stacked Components PF 38F 5070 Product Die/ Package Product Line Density Designator Designator Configuration Char 1 = Flash die #1 Char 2 = Flash die #2 Char 3 = ...
Page 97
Numonyx™ StrataFlash Wireless Memory (L18 AD-Mux) Table 47: 38F / 48F Density Decoder Code 0 No Die 1 32-Mbit 2 64-Mbit 3 128-Mbit 4 256-Mbit 5 512-Mbit 6 1-Gbit 7 2-Gbit 8 4-Gbit 9 8-Gbit A 16-Gbit B 32-Gbit ...
Page 98
Table 49: Voltage / NOR Flash CE# Configuration Decoder (Sheet I/O Voltage Code (Volt) R 3.0 1.8 Q 1.8 1.8 P 3.0 3.0 Table 50: Parameter / Mux Configuration Decoder Code, Mux Number of Flash Die Identification ...