MSC8101UG/D FREESCALE [Freescale Semiconductor, Inc], MSC8101UG/D Datasheet - Page 19

• Manufacturer Part Number: MSC8101UG/D
• Description: Network Digital Signal Processor
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

1.6 CPM Ports
The MSC8103 CPM supports the subset of MPC8260 signals as described below.
• The MSC8103 CPM includes the following set of communication controllers:
• Two full-duplex fast serial communications controllers (FCCs) that support:
• One FCC that operates with the TSA only
• Two multi-channel controllers (MCCs) that together can handle up to 256 HDLC/transparent channels at 64
• Two full-duplex serial communications controllers (SCCs) that support the following protocols:
• Two additional SCCs that operate with the TSA only
• Two full-duplex serial management controllers (SMCs) that support the following protocols:
• Serial peripheral interface (SPI) support for master or slave operation
• Inter-integrated circuit (I
• Time-slot assigner (TSA) that supports multiplexing from any of the SCCs, FCCs, SMCs, and two MCCs onto
The individual sets of externals signals associated with a specific protocol and data transfer mode are multiplexed
across any or all of the ports, as shown in Figure 1-2. The following sections describe the signals supported by
Ports A–D.
Freescale Semiconductor
— Asynchronous transfer mode (ATM) through a UTOPIA 8 interface (FCC1 only)—The MSC8103 can
— IEEE 802.3/Fast Ethernet through a Media-Independent Interface (MII)
— High-level data link control (HDLC) Protocol:
— Transparent mode serial operation
Kbps each, multiplexed on up to four TDM interfaces
— IEEE 802.3/fast Ethernet through a media-independent interface (MII)
— HDLC Protocol:
— Synchronous data link control (SDLC)
— LocalTalk (HDLC-based local area network protocol)
— Universal asynchronous receiver/transmitter (UART)
— Synchronous UART (1x clock mode)
— Binary synchronous (BISYNC) communication
— Transparent mode serial operation
— General circuit interface (GCI)/integrated services digital network (ISDN) monitor and C/I channels (TSA
— UART
— Transparent mode serial operation
four time-division multiplexed (TDM) interfaces. The TSA uses two serial interfaces (SI1 and SI2). SI1 uses
TDMA1 which supports both serial and nibble mode. SI2 does not support nibble mode and includes TDMB2,
TDMC2, and TDMD2, which operate only in serial mode.
operate as one of the following:
°
°
°
°
°
°
°
only)
UTOPIA slave device
UTOPIA multi-PHY master device using direct polling for up to 4 PHY devices
UTOPIA multi-PHY master device using multiplex polling that can address up to 31 PHY devices at addresses 0–30
(address 31 is reserved as a null port).
Serial mode—Transfers data one bit at a time
Nibble mode—Transfers data four bits at a time
Serial mode—Transfers data one bit at a time
Nibble mode—Transfers data four bits at a time
2
C) bus controller
MSC8103 Network Digital Signal Processor, Rev. 11
CPM Ports
1-15