MSC8101UG/D FREESCALE [Freescale Semiconductor, Inc], MSC8101UG/D Datasheet - Page 21

• Manufacturer Part Number: MSC8101UG/D
• Description: Network Digital Signal Processor
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Freescale Semiconductor
Purpose I/O
General-
PA27
PA26
PA25
PA24
PA23
FCC1: RXSOC
UTOPIA slave
FCC1: RX_DV
MII
FCC1: RXCLAV
UTOPIA slave
FCC1: RXCLAV
UTOPIA master, or
RXCLAV0
UTOPIA master, Multi-PHY, direct
polling
FCC1: RX_ER
MII
FCC1: TXD0
UTOPIA
SDMA: MSNUM0
FCC1: TXD1
UTOPIA
SDMA: MSNUM1
FCC1: TXD2
UTOPIA
Peripheral Controller:
Name
Dedicated Signal
Protocol
MSC8103 Network Digital Signal Processor, Rev. 11
Table 1-7.
Dedicated
Direction
I/O Data
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Port A Signals (Continued)
FCC1: UTOPIA Receive Start of Cell
Asserted by the MSC8103 (UTOPIA slave) for an external PHY when
RXD[0–7] contains the first valid byte of the cell.
FCC1: Media Independent Interface Receive Data Valid
Asserted by an external fast Ethernet PHY to indicate that valid data is
being sent. The presence of carrier sense but not RX_DV indicates
reception of broken packet headers, probably due to bad wiring or a bad
circuit.
FCC1: UTOPIA Slave Receive Cell Available
Asserted by the MSC8103 (UTOPIA slave PHY) when one complete
ATM cell is available for transfer.
FCC1: UTOPIA Master Receive Cell Available
Asserted by an external PHY when one complete ATM cell is available
for transfer.
FCC1: UTOPIA Master Receive Cell Available 0 Direct Polling
Asserted by an external PHY when one complete ATM cell is available
for transfer.
FCC1: Media Independent Interface Receive Error
Asserted by an external fast Ethernet PHY to indicate a receive error,
which often indicates bad wiring.
FCC1: UTOPIA Transmit Data Bit 0
The MSC8103 outputs ATM cell octets (UTOPIA interface data) on
TXD[0–7]. TXD0 is the least significant bit. When no ATM data is
available, idle cells are inserted. A cell is 53 bytes.
Module Serial Number Bit 0
The MSNUM has 6 bits that identify devices using the serial DMA
(SDMA) modules. MSNUM[0–4] is the sub-block code of the current
peripheral controller using SDMA. MSNUM5 indicates the section,
transmit (0) or receive (1), that is active during the transfer. The
information is recorded in the SDMA transfer error registers.
FCC1: UTOPIA Transmit Data Bit 1
The MSC8103 outputs ATM cell octets (UTOPIA interface data) on
TXD[0–7]. This is bit 1 of the transmit data. TXD7 is the most significant
bit. When no ATM data is available, idle cells are inserted. A cell is 53
bytes.
Module Serial Number Bit 1
The MSNUM has 6 bits that identify devices using the serial DMA
(SDMA) modules. MSNUM[0–4] is the sub-block code of the current
peripheral controller using SDMA. MSNUM5 indicates the section,
transmit (0) or receive (1), that is active during the transfer. The
information is recorded in the SDMA transfer error registers.
FCC1: UTOPIA Transmit Data Bit 2
The MSC8103 outputs ATM cell octets (UTOPIA interface data) on
TXD[0–7]. This is bit 2 of the transmit data. TXD7 is the most significant
bit. When no ATM data is available, idle cells are inserted. A cell is 53
bytes.
Description
CPM Ports
1-17