MSC8101UG/D FREESCALE [Freescale Semiconductor, Inc], MSC8101UG/D Datasheet - Page 40

• Manufacturer Part Number: MSC8101UG/D
• Description: Network Digital Signal Processor
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Signals/Connections
1.7 JTAG Test Access Port Signals
The MSC8103 supports the standard set of Test Access Port (TAP) signals defined by IEEE 1149.1 Standard Test
Access Port and Boundary-Scan Architecture specification and described in Table 1-11.
1.8 Reserved Signals
1-36
TEST
THERM[1–2]
SPARE1, 5
Signal Name
Signal Name
TRST
TDO
TMS
TCK
TDI
Output
Type
Type
Input
Input
Input
Input
Input
—
—
MSC8103 Network Digital Signal Processor, Rev. 11
Table 1-11.
Test Clock
A test clock signal for synchronizing JTAG test logic.
Test Data Input
A test data serial signal for test instructions and data. TDI is sampled on the rising edge of TCK and
has an internal pull-up resistor.
Test Data Output
A test data serial signal for test instructions and data. TDO can be tri-stated. The signal is actively
driven in the shift-IR and shift-DR controller states and changes on the falling edge of TCK.
Test Mode Select
Sequences the test controller’s state machine, is sampled on the rising edge of TCK, and has an
internal pull-up resistor.
Test Reset
Asynchronously initializes the test controller, has an internal pull-up resistor, and must be asserted
after power up.
Test
Used for manufacturing testing. You must connect this input to GND.
Leave disconnected.
Spare Pins
Leave disconnected for backward compatibility with future revisions of this device.
Table 1-12.
JTAG Test Access Port Signals
Reserved Signals
Signal Description
Signal Description
Freescale Semiconductor