MSC8101UG/D FREESCALE [Freescale Semiconductor, Inc], MSC8101UG/D Datasheet - Page 48

• Manufacturer Part Number: MSC8101UG/D
• Description: Network Digital Signal Processor
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Physical and Electrical Specifications
2.6.3
2-8
Phase Jitter between BCLK and DLLIN
CLKIN frequency
CLKIN slope
DLLIN slope
CLKOUT frequency jitter
Delay between CLKOUT and DLLIN
Notes:
Figure 2-6.
1.
2.
PORESET/TRST asserted
PORESET/TRST asserted
Clocking and Timing Characteristics
Low CLKIN frequency causes poor PLL performance. Choose a CLKIN frequency high enough to keep the frequency after the
predivider (SPLLMFCLK) higher than 18 MHz.
CLKIN should have a 50% ± 5% duty cycle.
1,2
Figure 2-5.
Start-Up Sequence with V
Characteristic
V
V
DDH
DDH
1.06 V
1.6 V
1.06 V
o.5 V
3.3 V
1.6 V
3.3 V
applied
applied
Start-Up Sequence with CLKIN Started After V
MSC8103 Network Digital Signal Processor, Rev. 11
V
DD
Table 2-10.
applied
DDH
Raised Before V
System Clock Parameters
CLKIN starts toggling
V
V
CLKIN starts toggling
Minimum
DDH
DD
1
V
18
—
—
—
—
—
= Nominal
DD
= Nominal
applied
DD
V
V
PORESET/TRST deasserted
with CLKIN Started Before V
DDH
DD
1
= Nominal
= Nominal
DDH
(0.01/CLKOUT) + CLKIN jitter
PORESET/TRST Deasserted
and Before V
V
V
DD
DDH
Maximum
Nominal
100
Nominal
V
0.5
V
Time
5
2
5
DD
DDH
Time
Freescale Semiconductor
Nominal
Nominal
DD
DD
= 0.5 V
Unit
MHz
ns
ns
ns
ns
ns