MSC8101UG/D FREESCALE [Freescale Semiconductor, Inc], MSC8101UG/D Datasheet - Page 24

• Manufacturer Part Number: MSC8101UG/D
• Description: Network Digital Signal Processor
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Signals/Connections
1-20
Purpose I/O
General-
PA12
PA11
PA10
PA9
PA8
FCC1: RXD2
UTOPIA
SDMA: MSNUM3
FCC1: RXD1
UTOPIA
SDMA: MSNUM4
FCC1: RXD0
UTOPIA
SDMA: MSNUM5
SMC2: SMTXD
SI1 TDMA1: L1TXD0
TDM nibble
SMC2: SMRXD
SI1 TDMA1: L1RXD0
TDM nibble
SI1 TDMA1: L1RXD
TDM serial
Peripheral Controller:
Name
Dedicated Signal
Protocol
MSC8103 Network Digital Signal Processor, Rev. 11
Table 1-7.
Dedicated
Direction
I/O Data
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Port A Signals (Continued)
FCC1: UTOPIA Receive Data Bit 2
The MSC8103 inputs ATM cell octets (UTOPIA interface data) on
RXD[0–7]. This is bit 2 of the receive data. RXD7 is the most significant
bit. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0–7] is
tri-stated, enabled only when RXENB is asserted.
Module Serial Number Bit 3
The MSNUM has 6 bits that identify devices using the serial DMA
(SDMA) modules. MSNUM[0–4] is the sub-block code of the current
peripheral controller using SDMA. MSNUM5 indicates the section,
transmit (0) or receive (1), that is active during the transfer. The
information is recorded in the SDMA transfer error registers.
FCC1: UTOPIA RX Receive Data Bit 1
The MSC8103 inputs ATM cell octets (UTOPIA interface data) on
RXD[0–7]. This is bit 1 of the receive data. RXD7 is the most significant
bit. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0–7] is
tri-stated, enabled only when RXENB is asserted.
Module Serial Number Bit 4
The MSNUM has 6 bits that identify devices using the serial DMA
(SDMA) modules. MSNUM[0–4] is the sub-block code of the current
peripheral controller using SDMA. MSNUM5 indicates the section,
transmit (0) or receive (1), that is active during the transfer. The
information is recorded in the SDMA transfer error registers.
FCC1: UTOPIA RX Receive Data Bit 0
The MSC8103 inputs ATM cell octets (UTOPIA interface data) on
RXD[0–7]. RXD0 is the least significant bit of the receive data. A cell is
53 bytes. To support Multi-PHY configurations, RXD[0–7] is tri-stated,
enabled only when RXENB is asserted.
Module Serial Number Bit 5
The MSNUM has 6 bits that identify devices using the serial DMA
(SDMA) modules. MSNUM[0–4] is the sub-block code of the current
peripheral controller using SDMA. MSNUM5 indicates the section,
transmit (0) or receive (1), that is active during the transfer. The
information is recorded in the SDMA transfer error registers.
SMC2: Serial Management Transmit Data
The SMC interface consists of SMTXD, SMRXD, SMSYN, and a clock.
Not all signals are used for all applications. SMCs are full-duplex ports
that supports three protocols or modes: UART, transparent, or general-
circuit interface (GCI). See also PC15.
Time-Division Multiplexing A1: Layer 1 Transmit Data Bit 0
L1TXD0 is the least significant bit of the TDM nibble data.
SMC2: Serial Management Receive Data
The SMC interface consists of SMTXD, SMRXD, SMSYN, and a clock.
Not all signals are used for all applications. SMCs are full-duplex ports
that supports three protocols or modes: UART, transparent, or general-
circuit interface (GCI).
Time-Division Multiplexing A1: Layer 1 Nibble Receive Data Bit 0
L1RXD0 is the least significant bit received in nibble mode.
Time-Division Multiplexing A1: Layer 1 Serial Receive Data
TDMA1 receives serial data from L1RXD.
Description
Freescale Semiconductor