A400CB10RC AMD [Advanced Micro Devices], A400CB10RC Datasheet - Page 11

• Manufacturer Part Number: A400CB10RC
• Description: 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 1.8 Volt-only Super Low Voltage Flash Memory
• Manufacturer: AMD [Advanced Micro Devices]

DEVICE BUS OPERATIONS
This section describes the requirements and use of the de-
vice bus operations, which are initiated through the internal
command register. The command register itself does not oc-
cupy any addressable memory location. The register is com-
posed of latches that store the commands, along with the
address and data information needed to execute the com-
Legend:
L = Logic Low = V
Notes:
1. Addresses are A17:A0 in word mode (BYTE# = V
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins
DQ15–DQ0 operate in the byte or word configuration. If the
BYTE# pin is set at logic ‘1’, the device is in word configura-
tion, DQ15–DQ0 are active and controlled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte con-
figuration, and only data I/O pins DQ0–DQ7 are active and
controlled by CE# and OE#. The data I/O pins DQ8–DQ14
are tri-stated, and the DQ15 pin is used as an input for the
LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive
the CE# and OE# pins to V
selects the device. OE# is the output control and gates array
data to the output pins. WE# should remain at V
BYTE# pin determines whether the device outputs array
data in words or bytes.
The internal state machine is set for reading array data upon
device power-up, or after a hardware reset. This ensures
January 23, 2007 Am29SL400C_00_A6
Read
Write
Standby
Output Disable
Reset
Sector Protect (Note 2)
Sector Unprotect (Note 2)
Temporary Sector Unprotect
Protection/Unprotection” section.
Operation
IL
, H = Logic High = V
IL
. CE# is the power control and
V
0.2 V
CE#
CC
X
X
IH
Table 1. Am29SL400C Device Bus Operations
L
L
L
L
L
, V
±
ID
OE#
= 10 ± 1.0 V, X = Don’t Care, A
H
X
H
X
H
H
X
L
WE#
IH
H
X
H
X
X
D A T A
L
L
L
), A17:A-1 in byte mode (BYTE# = V
IH
RESET#
. The
V
0.2 V
Am29SL400C
V
V
V
CC
H
H
H
L
ID
ID
ID
±
S H E E T
Sector Address, A6
Sector Address, A6
mand. The contents of the register serve as inputs to the in-
ternal state machine. The state machine outputs dictate the
function of the device.
tions, the inputs and control levels they require, and the re-
sulting output. The following subsections describe each of
these operations in further detail.
that no spurious alteration of the memory content occurs
during the power transition. No command is necessary in
this mode to obtain array data. Standard microprocessor
read cycles that assert valid addresses on the device ad-
dress inputs produce valid data on the device data outputs.
The device remains enabled for read access until the com-
mand register contents are altered.
See
Refer to the AC Read Operations table for timing specifica-
tions and to
I
current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which includes
programming data to the device and erasing sectors of
memory), the system must drive WE# and CE# to V
OE# to V
For program operations, the BYTE# pin determines whether
the device accepts program data in bytes or words. Refer
to
CC1
= H, A1 = H,
= L, A1 = H,
Addresses
IN
Word/Byte Configuration‚ on page 9
(Note 1)
A0 = L
A0 = L
= Address In, D
in the DC Characteristics table represents the active
A
A
A
Reading Array Data‚ on page 15
X
X
X
IN
IN
IN
IH
.
Figure 14‚ on page 28
IL
).
IN
High-Z
High-Z
High-Z
DQ0–
D
DQ7
D
D
D
D
OUT
= Data In, D
IN
IN
IN
IN
Table 1
BYTE#
High-Z
High-Z
High-Z
D
= V
D
D
OUT
X
X
IN
IN
OUT
IH
lists the device bus opera-
= Data Out
for the timing diagram.
DQ8–DQ15
DQ8–DQ14 = High-Z,
for more information.
for more information.
DQ15 = A-1
BYTE#
High-Z
High-Z
High-Z
High-Z
= V
X
X
IL
IL
, and
9