A400CB10RC AMD [Advanced Micro Devices], A400CB10RC Datasheet - Page 12

• Manufacturer Part Number: A400CB10RC
• Description: 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 1.8 Volt-only Super Low Voltage Flash Memory
• Manufacturer: AMD [Advanced Micro Devices]

The device features an Unlock Bypass mode to facilitate
faster programming. Once the device enters the Unlock By-
pass mode, only two write cycles are required to program a
word or byte, instead of four. The
mand Sequence‚ on page 15
data to the device using both standard and Unlock Bypass
command sequences.
An erase operation can erase one sector, multiple sectors, or
the entire device.
page 11
pies. A sector address consists of the address bits required
to uniquely select a sector.
page 18
suspending/resuming the erase operation.
After the system writes the autoselect command sequence,
the device enters the autoselect mode. The system can then
read autoselect codes from the internal register (which is
separate from the memory array) on DQ7–DQ0. Standard
read cycle timings apply in this mode. Refer to
Mode‚ on page 11
page 15
I
current specification for the write mode. The
istics‚ on page 28
timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status bits
on DQ7–DQ0. Standard read cycle timings and I
specifications apply. Refer to
page 19
page 28
Standby Mode
When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode, cur-
rent consumption is greatly reduced, and the outputs are
placed in the high impedance state, independent of the OE#
input.
The device enters the CMOS standby mode when the CE#
and RESET# pins are both held at V
this is a more restricted voltage range than V
RESET# are held at V
vice will be in the standby mode, but the standby current will
be greater. The device requires standard access time (t
for read access when the device is in either of these standby
modes, before it is ready to read data.
The device also enters the standby mode when the RESET#
pin is driven low. Refer to the next section, RESET#: Hard-
ware Reset Pin.
10
CC2
in the DC Characteristics table represents the active
has details on erasing a sector or the entire chip, or
for more information.
for timing diagrams.
for more information, and to
indicate the address space that each sector occu-
and
contains timing specification tables and
Table 2 on page 11
IH
Autoselect Command Sequence‚ on
, but not within V
has details on programming
Command Definitions‚ on
Write Operation Status‚ on
Word/Byte Program Com-
AC Characteristics‚ on
CC
± 0.2 V. (Note that
CC
and
± 0.2 V, the de-
IH
AC Character-
.) If CE# and
Table 3 on
D A T A
Autoselect
CC
read
Am29SL400C
CE
)
S H E E T
If the device is deselected during erasure or programming,
the device draws active current until the operation is com-
pleted.
I
standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy
consumption. The device automatically enables this mode
when addresses remain stable for t
matic sleep mode is independent of the CE#, WE#, and OE#
control signals. Standard address access timings provide
new data when addresses are changed. While in sleep
mode, output data is latched and always available to the sys-
tem. I
tomatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting
the device to reading array data. When the RESET# pin is
driven low for at least a period of t
ately terminates any operation in progress, tristates all out-
put pins, and ignores all read/write commands for the
duration of the RESET# pulse. The device also resets the in-
ternal state machine to reading array data. The operation
that was interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure data
integrity.
Current is reduced for the duration of the RESET# pulse.
When RESET# is held at V
CMOS standby current (I
not within V
The RESET# pin may be tied to the system reset circuitry. A
system reset would thus also reset the Flash memory, en-
abling the system to read the boot-up firmware from the
Flash memory.
If RESET# is asserted during a program or erase operation,
the RY/BY# pin remains a 0 (busy) until the internal reset op-
eration is complete, which requires a time of t
Embedded Algorithms). The system can thus monitor
RY/BY# to determine whether the reset operation is com-
plete. If RESET# is asserted when a program or erase oper-
ation is not executing (RY/BY# pin is 1), the reset operation
is completed within a time of t
Algorithms). The system can read data t
SET# pin returns to V
Refer to the AC Characteristics tables for RESET# parame-
ters and to
Output Disable Mode
When the OE# input is at V
abled. The output pins are placed in the high impedance
state.
CC3
in
CC4
DC Characteristics‚ on page 24
in the DC Characteristics table represents the au-
Figure 15‚ on page 29
SS
±0.2 V, the standby current is greater.
IH
.
CC4
Am29SL400C_00_A6 January 23, 2007
IH
). If RESET# is held at V
, output from the device is dis-
SS
READY
±0.2 V, the device draws
for the timing diagram.
RP
ACC
(not during Embedded
, the device immedi-
+ 50 ns. The auto-
RH
represents the
READY
after the RE-
(during
IL
but