SC18IM700IPW PHILIPS [NXP Semiconductors], SC18IM700IPW Datasheet - Page 11

• Manufacturer Part Number: SC18IM700IPW
• Description: Master I-2C - bus controller with UART interface
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
SC18IM700_1
Product data sheet
9.2.2.4 Open-drain output configuration
9.2.3 Programmable I/O pins state register (IOState)
9.2.4 I
9.2.5 I
The open-drain output configuration turns off all pull-ups and only drives the pull-down
transistor of the port driver when the port latch contains a logic 0. To be used as a logic
output, a port configured in this manner must have an external pull-up, typically a resistor
tied to V
An open-drain port pin has a Schmitt triggered input that also has a glitch suppression
circuit.
When read, this register returns the actual state of all I/O pins. When written, each
register bit will be transferred to the corresponding I/O pin programmed as output.
Table 6:
The contents of the register represents the device’s own I
significant bit corresponds to the first bit received from the I
condition. A logic 1 in I2CAdr corresponds to a HIGH level on the I
corresponds to a LOW level on the I
be programmed with a ‘0’.
I2CAdr is not needed for device operation, but should be configured so that its address
does not conflict with an I
This register determines the serial clock frequency. The various serial rates are shown in
Table
I2CClkH determines the SCL HIGH period, and I2CClkL determines the SCL LOW period.
bit frequency
Bit
7:0
2
2
Fig 16. Open-drain output configuration
C-bus address register (I2CAdr)
C-bus clock rates (I2CClk)
7. The frequency can be determined using the following formula:
DD
.
Symbol
IOLevel
IOState - Programmable I/O pins state register (address 0x04h) bit description
=
pin latch data
---------------------------------------------------------------
2
I2CClkH
Rev. 01 — 28 February 2006
7.3728 10
Description
Set the logic level on the output pins.
Write to this register:
Read this register returns states of all pins.
2
C-bus device address used by the bus master.
logic 0 = set output pin to zero
logic 1 = set output pin to one
+
I2CClkL
6
2
C-bus. The least significant bit is not used, but should
input data
V
Master I
SS
2
C-bus controller with UART interface
glitch rejection
2
C-bus address. The most
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
2
C-bus after a START
SC18IM700
2
002aab883
GPIO pin
C-bus, and a logic 0
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