AMD-K6-2E/400AFR AMD [Advanced Micro Devices], AMD-K6-2E/400AFR Datasheet - Page 270

• Manufacturer Part Number: AMD-K6-2E/400AFR
• Manufacturer: AMD [Advanced Micro Devices]

AMD-K6™-2E Processor Data Sheet
13.5
Enter Stop Clock
State
Exit Stop Clock State
252
Stop Clock State
If the CLK signal is stopped while the AMD-K6-2E processor is
in the Stop Grant state, the processor enters the Stop Clock
state. Because all internal clocks and the PLL are not running
in the Stop Clock state, the Stop Clock state represents the
minimum-power state of all clock control states. The CLK signal
must be held Low while it is stopped.
The Stop Clock state cannot be entered from the Halt state.
INTR is the only input signal that is allowed to change states
while the processor is in the Stop Clock state. However, INTR is
not sampled until the processor returns to the Stop Grant state.
All other input signals must remain unchanged in the Stop
Clock state.
The AMD-K6-2E processor returns to the Stop Grant state from
the Stop Clock state after the CLK signal is started and the
internal PLL has stabilized. PLL stabilization is achieved after
the CLK signal has been running within its specification for a
minimum of 1.0 ms.
The frequency of CLK when exiting the Stop Clock state can be
different than the frequency of CLK when entering the Stop
Clock state.
The state of the BF[2:0] signals when exiting the Stop Clock
state is ignored because the BF[2:0] signals are only sampled
during the falling transition of RESET.
Preliminary Information
Clock Control
22529B/0—January 2000
Chapter 13