TDA9550 PHILIPS [NXP Semiconductors], TDA9550 Datasheet - Page 98

• Manufacturer Part Number: TDA9550
• Description: TV signal processor-Teletext decoder with embedded m-Controller
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
Notes
1. When the 3.3 V supply is present and the -Controller is active a ‘low-power start-up’ mode can be activated. When
2. On set AGC.
3. This parameter is not tested during production and is just given as application information for the designer of the
4. Loop bandwidth BL = 60 kHz (natural frequency fN = 15 kHz; damping factor d = 2; calculated with top sync level as
5. The IF-PLL demodulator uses an internal VCO (no external LC-circuit required) which is calibrated by means of a
6. This parameter is not tested during production but is guaranteed by the design and qualified by means of matrix
7. Measured at 10 mV (RMS) top sync input signal.
8. Via this pin both the demodulated IF signal and the selected CVBS (or Y+C) signal can be supplied to the output.
9. So called projected zero point, i.e. with switched demodulator.
2000 Jun 22
B
C.7.1
C.7.2
C.7.3
C.7.4
C.7.5
C.7.6
F
C.8.1
C.8.2
P
C.9.1
C.9.2
IXED BEAM CURRENT SWITCH
EAM CURRENT LIMITING
EAK WHITE LIMITER AND SOFT CLIPPING
TV signal processor-Teletext decoder with
embedded -Controller
NUMBER
all sub-address bytes have been sent and the POR and XPR flags have been cleared the horizontal output can be
switched-on via the STB-bit (subaddress 24H). In this condition the horizontal drive signal has the nominal T
the T
(e.g. closing of the second loop) is continued.
television receiver.
FPLL input signal level).
digital control circuit which uses the clock frequency of the -Controller as a reference. The required IF frequency for
the various standards is set via the IFA-IFC bits in subaddress 27H. When the system is locked the resulting IF
frequency is very accurate with a deviation from the nominal value of less than 25 kHz.
batches which are made in the pilot production period.
The selection between both signals is realised by means of the SVO bit in subaddress 22H.
ON
grows gradually from zero to the nominal value. As soon as the 8 V supply is present the switch-on procedure
contrast reduction starting
voltage
voltage difference for full contrast
reduction
brightness reduction starting
voltage
voltage difference for full
brightness reduction
internal bias voltage
maximum allowable current
discharge current during
switch-off
discharge time of picture tube
CVBS/Y-input signal amplitude
at which peak white limiter is
activated (black-to-white value)
soft clipper gain reduction
PARAMETER
-
OFF
;
NOTE
;
NOTES
62
63
PWL range (15 steps); at
max. contrast
maximum contrast; note 64,
see Fig.47
AND
64
CONDITIONS
98
TDA955X/6X/8X PS/N1 series
0.85
0.55
MIN.
Tentative Device Specification
2.8
1.8
1.7
0.9
3.3
tbf
1.0
38
8
TYP.
1.15
0.85
MAX.
V
V
V
V
V
mA
ms
dB
mA
V
OFF
UNIT
and