ADV7181 AD [Analog Devices], ADV7181 Datasheet - Page 58

• Manufacturer Part Number: ADV7181
• Description: Multiformat SDTV Video Decoder
• Manufacturer: AD [Analog Devices]

ADV7181B
PIXEL PORT CONFIGURATION
The ADV7181B has a very flexible pixel port that can be config-
ured in a variety of formats to accommodate downstream ICs.
Table 77 and Table 78 summarize the various functions that the
ADV7181B pins can have in different modes of operation.
The ordering of components , for example, Cr versus Cb,
CHA/B/C, can be changed. Refer to the SWPC Swap Pixel
Cr/Cb, Address 0x27 [7] section. Table 77 indicates the default
positions for the Cr/Cb components.
OF_SEL[3:0] Output Format Selection, Address 0x03 [5:2]
The modes in which the ADV7181B pixel port can be configured
are under the control of OF_SEL[3:0]. See Table 78 for details.
The default LLC frequency output on the LLC1 pin is approxi-
mately 27 MHz. For modes that operate with a nominal data
rate of 13.5 MHz (0001, 0010), the clock frequency on the LLC1
pin stays at the higher rate of 27 MHz. For information on
outputting the nominal 13.5 MHz clock on the LLC1 pin, see
the LLC1 Output Selection, LLC_PAD_SEL[2:0],
Address 0x8F [6:4] section.
SWPC Swap Pixel Cr/Cb, Address 0x27 [7]
This bit allows Cr and Cb samples to be swapped.
When SWPC is 0 (default), no swapping is allowed.
When SWPC is 1, the Cr and Cb values can be swapped.
Table 77. P15–P0 Output/Input Pin Mapping
Format and Mode
Video Out, 8-Bit, 4:2:2
Video Out, 16-Bit, 4:2:2
Table 78. Standard Definition Pixel Port Modes
OF_SEL[3:0]
0010
0011
0110-1111
Format
16-Bit @LLC2 4:2:2
8-Bit @LLC1 4:2:2 (default)
Reserved
15
14
13
YCrCb[7:0]OUT
Y[7:0]OUT
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11
LLC1 Output Selection, LLC_PAD_SEL[2:0],
Address 0x8F [6:4]
The following I
LLC1 (nominally at 27 MHz) and LLC2 (nominally at
13.5 MHz).
The LLC2 signal is useful for LLC2-compatible wide bus
(16-bit) output modes. See OF_SEL[3:0] Output Format
Selection, Address 0x03 [5:2] for additional information. The
LLC2 signal and data on the data bus are synchronized. By
default, the rising edge of LLC1/LLC2 is aligned with the Y data;
the falling edge occurs when the data bus holds C data. The
polarity of the clock, and therefore the Y/C assignments to the
clock edges, can be altered by using the Polarity LLC pin.
When LLC_PAD_SEL is 000, the output is nominally 27 MHz
LLC on the LLC1 pin (default).
When LLC_PAD_SEL is 101, the output is nominally 13.5 MHz
LLC on the LLC1 pin.
10
Data Port Pins P[15:0]
P[15:8]
Y[7:0]
YCrCb[7:0]
9
8
2
C write allows the user to select between the
7
Reserved. Do not use.
6
P[15: 0]
5
CrCb[7:0] OUT
P[7: 0]
CrCb[7:0]
Three-State
4
3
2
1
0