ADV7181 AD [Analog Devices], ADV7181 Datasheet - Page 79

• Manufacturer Part Number: ADV7181
• Description: Multiformat SDTV Video Decoder
• Manufacturer: AD [Analog Devices]

Subaddress
0x34
0x35
0x36
0x37
Register
HS
Position
Control 1
HS
Position
Control 2
HS
Position
Control 3
Polarity
Bit Description
HSE[10:8]. HS end allows the
positioning of the HS output within
the video line.
Reserved
HSB[10:8]. HS begin allows the
positioning of the HS output within
the video line.
Reserved
HSB[7:0] See above, using HSB[10:0]
and HSE[10:0], the user can program
the position and length of HS output
signal.
HSE[7:0] See above.
PCLK. Sets the polarity of LLC1.
Reserved
PF. Sets the FIELD polarity.
Reserved
PVS. Sets the VS Polarity.
Reserved
PHS. Sets HS Polarity.
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7 6
0
0 0
0 0
0
1
0
0
5
0
0
0
0
1
4 3
0
0 0
0 0
0
Bits
0
0
1
2
0
0
0
0
1
0
1
0
0
0
0
0
0
0
1
Comments
pixels after the falling edge
of HSync
HS output starts HSB[10:0]
pixels after the falling edge
of HSync
Set to 0
Invert polarity
Normal polarity as per the
timing diagrams
Set to 0
Active high
Active low
HS output ends HSE[10:0]
Set to 0
Set to 0
Active high
Active low
Active high
Active low
Set to 0
Notes
Using HSB and HSE
the user can
program the
position and length
of the output HSync
ADV7181B