ADV7181 AD [Analog Devices], ADV7181 Datasheet - Page 7

• Manufacturer Part Number: ADV7181
• Description: Multiformat SDTV Video Decoder
• Manufacturer: AD [Analog Devices]

TIMING SPECIFICATIONS
Guaranteed by characterization. At A
(operating temperature range, unless otherwise noted).
Table 3.
Parameter
SYSTEM CLOCK AND CRYSTAL
I
RESET FEATURE
CLOCK OUTPUTS
DATA AND CONTROL OUTPUTS
ANALOG SPECIFICATIONS
Guaranteed by characterization. At A
(operating temperature range, unless otherwise noted).
Table 4.
Parameter
CLAMP CIRCUITRY
2
C PORT
Nominal Frequency
Frequency Stability
SCLK Frequency
SCLK Min Pulse Width High
SCLK Min Pulse Width Low
Hold Time (Start Condition)
Setup Time (Start Condition)
SDA Setup Time
SCLK and SDA Rise Time
SCLK and SDA Fall Time
Setup Time for Stop Condition
Reset Pulse Width
LLC1 Mark Space Ratio
Data Output Transitional Time
Data Output Transitional Time
External Clamp Capacitor
Input Impedance
Large Clamp Source Current
Large Clamp Sink Current
Fine Clamp Source Current
Fine Clamp Sink Current
VDD
VDD
= 3.15 V to 3.45 V, D
= 3.15 V to 3.45 V, D
Symbol
Symbol
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
9
11
12
:t
10
Test Conditions
Clamps switched off
Rev. 0 | Page 7 of 96
VDD
VDD
Negative Clock Edge to start of valid
data. (t
End of valid data to negative clock
edge. (t
Test Conditions
= 1.65 V to 2.0 V, D
= 1.65 V to 2.0 V, D
ACCESS
HOLD
= t
= t
9
10
+ t
– t
12
11
)
)
VDDIO
VDDIO
= 3.0 V to 3.6 V, P
= 3.0 V to 3.6 V, P
Min
0.6
1.3
0.6
0.6
100
5
45:55
VDD
VDD
Min
Typ
27.00
0.6
= 1.65 V to 2.0 V
= 1.65 V to 2.0 V
0.75
0.75
Typ
0.1
10
60
60
Max
±50
400
300
300
55:45
3.4
2.4
ADV7181B
Max
Unit
MHz
ppm
kHz
µs
µs
µs
µs
ns
ns
ns
µs
ms
% Duty Cycle
ns
ns
Unit
µF
MΩ
mA
mA
µA
µA