DAC1208D650HN NXP [NXP Semiconductors], DAC1208D650HN Datasheet - Page 94

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DAC1208D650HN

Manufacturer Part Number
DAC1208D650HN
Description
Manufacturer
NXP [NXP Semiconductors]
Datasheet
NXP Semiconductors
16. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. Interpolation filter coefficients . . . . . . . . . . . . .26
Table 11. Inversion filter coefficients . . . . . . . . . . . . . . . .28
Table 12. DAC transfer function . . . . . . . . . . . . . . . . . . .28
Table 13. I
Table 14. I
Table 15. Digital offset adjustment . . . . . . . . . . . . . . . . .31
Table 16. Auxiliary DAC transfer function . . . . . . . . . . . .32
Table 17. Page 0 register allocation map . . . . . . . . . . . .38
Table 18. COMMON register (address 00h)
Table 19. TXCFG register (address 01h)
Table 20. PLLCFG register (address 02h)
Table 21. FREQNCO_LSB register (address 03h)
Table 22. FREQNCO_LISB register (address 04h)
Table 23. FREQNCO_UISB register (address 05h)
Table 24. FREQNCO_MSB register (address 06h)
Table 25. PHINCO_LSB register (address 07h)
Table 26. PHINCO_MSB register (address 08h)
Table 27. DAC_A_CFG_1 register (address 09h)
Table 28. DAC_A_CFG_2 register (address 0Ah)
Table 29. DAC_A_CFG_3 register (address 0Bh)
Table 30. DAC_B_CFG_1 register (address 0Ch)
Table 31. DAC_B_CFG_2 register (address 0Dh)
Table 32. DAC_B_CFG_3 register (address 0Eh)
Table 33. DAC_CFG register (address 0Fh)
DAC1208D650
Product data sheet
Read or Write mode access description . . . . .23
bit description . . . . . . . . . . . . . . . . . . . . . . . . .40
bit description . . . . . . . . . . . . . . . . . . . . . . . . .40
bit description . . . . . . . . . . . . . . . . . . . . . . . . .41
bit description . . . . . . . . . . . . . . . . . . . . . . . . .41
bit description . . . . . . . . . . . . . . . . . . . . . . . . .41
bit description . . . . . . . . . . . . . . . . . . . . . . . . .41
bit description . . . . . . . . . . . . . . . . . . . . . . . . .42
bit description . . . . . . . . . . . . . . . . . . . . . . . . .42
bit description . . . . . . . . . . . . . . . . . . . . . . . . .42
bit description . . . . . . . . . . . . . . . . . . . . . . . . .42
bit description . . . . . . . . . . . . . . . . . . . . . . . . .42
bit description . . . . . . . . . . . . . . . . . . . . . . . . .42
bit description . . . . . . . . . . . . . . . . . . . . . . . . .43
bit description . . . . . . . . . . . . . . . . . . . . . . . . .43
bit description . . . . . . . . . . . . . . . . . . . . . . . . .43
Ordering information . . . . . . . . . . . . . . . . . . . . .2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . .6
Thermal characteristics . . . . . . . . . . . . . . . . . . .6
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .7
Digital Layer Processing Latency . . . . . . . . . . .12
Number of bytes to be transferred . . . . . . . . . .23
SPI timing characteristics . . . . . . . . . . . . . . . .24
O(fs)
O(fs)
coarse adjustment . . . . . . . . . . . . . . . . . .30
fine adjustment . . . . . . . . . . . . . . . . . . . .30
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 14 December 2010
2×, 4× or 8× interpolating DAC with JESD204A interface
Table 34. DAC_CURRENT_0 register (address 11h)
Table 35. DAC_CURRENT_1 register (address 12h)
Table 36. DAC_CURRENT_2 register (address 13h)
Table 37. DAC_CURRENT_3 register (address 14h)
Table 38. DAC_SEL_PH_FINE register (address 15h)
Table 39. PHASECORR_CNTRL0 register (address 16h)
Table 40. PHASECORR_CNTRL1 register (address 17h)
Table 41. DAC_A_AUX_MSB register (address 1Ah)
Table 42. DAC_A_AUX_LSB register (address 1Bh)
Table 43. DAC_B_AUX_MSB register (address 1Ch)
Table 44. DAC_B_AUX_LSB register (address 1Dh)
Table 45. DAC_B_AUX_LSB register (address 1Dh)
Table 46. Bias current control table . . . . . . . . . . . . . . . . . 45
Table 47. Page 1 register allocation map . . . . . . . . . . . . 46
Table 48. MDS_MAIN register (address 00h)
Table 49. MDS_WIN_PERIOD_A register (address 01h)
Table 50. MDS_WIN_PERIOD_B register (address 02h)
Table 51. MDS_MISCCNTRL0 register (address 03h)
Table 52. MDS_MAN_ADJUSTDLY register (address 04h)
Table 53. MDS_AUTO_CYCLES register (address 05h)
Table 54. MDS_MISCCNTRL1 register (address 06h)
Table 55. MDS_ADJDELAY register (address 08h)
Table 56. MDS_STATUS0 register (address 09h)
Table 57. MDS_STATUS1 register (address 0Ah)
Table 58. PAGE_ADDRESS register (address 1Fh)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 43
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 43
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 43
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 44
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 44
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 44
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 44
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 44
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 44
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 44
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 44
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 47
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 47
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 47
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 48
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 48
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 48
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 48
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 49
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 49
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 50
DAC1208D650
© NXP B.V. 2010. All rights reserved.
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