ADSP-BF561SBBCZ-5A2 AD [Analog Devices], ADSP-BF561SBBCZ-5A2 Datasheet - Page 12

• Manufacturer Part Number: ADSP-BF561SBBCZ-5A2
• Manufacturer: AD [Analog Devices]

ADSP-BF561
preserved. Since V
external pins three-state, unless otherwise specified. This allows
other devices that may be connected to the processor to have
power still applied without drawing unwanted current. The
internal supply regulator can be woken up by asserting the
RESET pin.
Power Savings
As shown in
power domains. The use of multiple power domains maximizes
flexibility, while maintaining compliance with industry stan-
dards and conventions. By isolating the internal logic of the
ADSP-BF561 into its own power domain, separate from the I/O,
the processor can take advantage of Dynamic Power Manage-
ment, without affecting the I/O devices. There are no
sequencing requirements for the various power domains.
Table 4. ADSP-BF561 Power Domains
The power dissipated by a processor is largely a function of the
clock frequency of the processor and the square of the operating
voltage. For example, reducing the clock frequency by 25%
results in a 25% reduction in dynamic power dissipation, while
reducing the voltage by 25% reduces dynamic power dissipation
by more than 40%. Further, these power savings are additive, in
that if the clock frequency and supply voltage are both reduced,
the power savings can be dramatic.
The dynamic power management feature of the ADSP-BF561
allows both the processor’s input voltage (V
quency (f
The savings in power dissipation can be modeled using the
power savings factor and % power savings calculations.
The power savings factor is calculated as:
where the variables in the equations are:
The percent power savings is calculated as:
Power Domain
All internal logic
I/O
f
f
V
V
t
t
% power savings
CCLKNOM
CCLKRED
NOM
RED
DDINTNOM
DDINTRED
is the duration running at f
CCLK
is the duration running at f
power savings factor
=
) to be dynamically controlled.
is the reduced core clock frequency
Table
is the nominal core clock frequency
-------------------- -
f
is the reduced internal supply voltage
f
is the nominal internal supply voltage
CCLKNOM
CCLKRED
DDEXT
4, the ADSP-BF561 supports two different
=
is still supplied in this mode, all of the
×
(
1 power savings factor
⎛
⎝
------------------------- -
V
V
–
DDINTNOM
DDINTRED
CCLKRED
CCLKNOM
⎞
⎠
2
×
⎛
⎝
DDINT
---------- -
t
t
NOM
RED
) and clock fre-
⎞
⎠
)
×
Rev. B | Page 12 of 64 | June 2007
V
V
V
100%
DDINT
DDEXT
DD
Range
100µF
VOLTAGE REGULATION
The ADSP-BF561 processor provides an on-chip voltage regula-
tor that can generate processor core voltage levels 0.85 V to
1.30 V (within a specified tolerance, see Operating Conditions)
from an external 2.25 V to 3.6 V supply.
ical external components required to complete the power
management system. The regulator controls the internal logic
voltage levels and is programmable with the voltage regulator
control register (VR_CTL) in increments of 50 mV. To reduce
standby power consumption, the internal voltage regulator can
be programmed to remove power to the processor core while
keeping I/O power (V
state, V
external buffers. The voltage regulator can be activated from
this power-down state by asserting RESET, which will then ini-
tiate a boot sequence. The regulator can also be disabled and
bypassed at the user’s discretion.
The internal voltage regulation feature is not available on auto-
motive grade models. External voltage regulation is required to
ensure correct operation of these parts.
Voltage Regulator Layout Guidelines
Regulator external component placement, board routing, and
bypass capacitors all have a significant effect on noise injected
into the other analog circuits on-chip. The VROUT1-0 traces
and voltage regulator external components should be consid-
ered as noise sources when doing board layout and should not
be routed or placed near sensitive circuits or components on the
board. All internal and I/O power supplies should be well
bypassed with bypass capacitors placed as close to the
ADSP-BF561 processors as possible.
2.25V TO 3.6V
INPUT VOLTAGE
RANGE
NOTE: DESIGNER SHOULD MINIMIZE
TRACE LENGTH TO FDS9431A.
+
LOW ESR
DDEXT
10µF
can still be applied, thus eliminating the need for
100nF
(LOW-INDUCTANCE)
FDS9431A
Figure 4. Voltage Regulator Circuit
V
DDEXT
DDEXT
) supplied. While in the hibernate
ZHCS1000
INDUCTANCE WIRE
SHORT AND LOW-
10µH
SET OF DECOUPLING
CAPACITORS
100µF
100µF
+
+
Figure 4
V
V
VR
VR
GND
shows the typ-
DDEXT
DDINT
OUT
OUT