ADSP-BF561SBBCZ-5A2 AD [Analog Devices], ADSP-BF561SBBCZ-5A2 Datasheet - Page 26

• Manufacturer Part Number: ADSP-BF561SBBCZ-5A2
• Manufacturer: AD [Analog Devices]

ADSP-BF561
SDRAM Interface Timing
Table 19. SDRAM Interface Timing
1
2
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
t
Refer to
Command pins include: SRAS, SCAS, SWE, SDQM, SMS3–0, SA10, SCKE.
SSDAT
HSDAT
SCLK
SCLKH
SCLKL
DCAD
HCAD
DSDAT
ENSDAT
Table 15 on Page 22
DATA Setup Before CLKOUT
DATA Hold After CLKOUT
CLKOUT Period
CLKOUT Width High
CLKOUT Width Low
Command, ADDR, Data Delay After CLKOUT
Command, ADDR, Data Hold After CLKOUT
Data Disable After CLKOUT
Data Enable After CLKOUT
CLKOUT
DATA (IN)
DATA(OUT)
CMND ADDR
for maximum f
(OUT)
1
SCLK
at various V
t
SSDAT
NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
DDINT
.
Rev. B | Page 26 of 64 | June 2007
2
Figure 11. SDRAM Interface Timing
2
t
DCAD
t
SCLK
t
t
ENSDAT
HSDAT
t
t
DCAD
HCAD
t
SCLKL
Min
1.5
0.8
7.5
2.5
2.5
0.8
1.0
t
t
D SDA T
SCLKH
t
HCAD
Max
4.0
4.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns