ADSP-BF561SBBCZ-5A2 AD [Analog Devices], ADSP-BF561SBBCZ-5A2 Datasheet - Page 43

• Manufacturer Part Number: ADSP-BF561SBBCZ-5A2
• Manufacturer: AD [Analog Devices]

The time for the voltage on the bus to decay by ΔV is dependent
on the capacitive load C
can be approximated by the equation:
The time t
ΔV equal to 0.5 V for V
The time t
nal switches, to when the output voltage decays ΔV from the
measured output high or output low voltage.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate t
to be the difference between the ADSP-BF561 processor’s out-
put voltage and the input threshold for the device requiring the
hold time. C
the total leakage or three-state current (per data line). The hold
time will be t
fied in the
for an SDRAM write cycle as shown in
ing on Page
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see
nal) = 2.5 V/3.3 V.
how output rise time varies with capacitance. The delay and
hold specifications given should be derated by a factor derived
from these figures. The graphs in these figures may not be linear
outside the ranges shown.
(MEASURED)
(MEASURED)
t
DIS
V
V
OUTPUT
Figure 37. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
OH
OL
PIN
OUTPUT STOPS DRIVING
TO
DECAY
DIS
Timing Specifications on Page 22
_
26).
L
MEASURED
DECAY
is the total bus capacitance (per data line), and I
DECAY
is calculated with test loads C
plus the various output disable times as speci-
Figure 36. Output Enable/Disable
REFERENCE
t
Figure 38
V
using the equation given above. Choose ΔV
DIS_MEASURED
V
is the interval from when the reference sig-
OH
OL
SIGNAL
t
t
Figure
DECAY
DECAY
(MEASURED)
(MEASURED) + V
DDEXT
L
and the load current I
HIGH IMPEDANCE STATE
(nominal) = 2.5 V/3.3 V.
through
=
37). V
30pF
t
(
ENA
C
L
V
LOAD
Δ
V
Figure 45 on Page 44
OUTPUT STARTS DRIVING
50
) I
is 1.5 V for V
SDRAM Interface Tim-
⁄
L
t
ENA_MEASURED
V
L
V
(for example t
TRIP
TRIP
and I
t
L
TRIP
. This decay time
(LOW)
(HIGH)
V
V
OH
OL
L
(MEASURED)
(MEASURED)
, and with
DDEXT
V
Rev. B | Page 43 of 64 | June 2007
LOAD
(nomi-
show
DSDAT
L
is
Figure 38. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
Figure 39. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
Figure 40. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
14
12
10
12
10
12
10
8
6
4
2
0
8
6
4
2
0
8
6
4
2
0
0
0
0
50
50
50
for Driver A at V
for Driver A at V
for Driver B at V
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
100
100
100
RISE TIME
RISE TIME
RISE TIME
DDEXT
DDEXT
DDEXT
(max)
150
150
(min)
(min)
150
FALL TIME
FALL TIME
FALL TIME
ADSP-BF561
200
200
200
250
250
250