ADSP-BF561SBBCZ-5A2 AD [Analog Devices], ADSP-BF561SBBCZ-5A2 Datasheet - Page 30

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ADSP-BF561SBBCZ-5A2

Manufacturer Part Number
ADSP-BF561SBBCZ-5A2
Description
Manufacturer
AD [Analog Devices]
Datasheet
ADSP-BF561
PPIxCLK
POLC = 0
PPIxCLK
POLC = 1
PPxSYNC1
PPIxSYNC2
PPIx_DATA
PPIxCLK
POLC = 0
PPIxCLK
POLC = 1
PPIxSYNC1
PPIxSYNC2
PPIx_ D ATA
POLS = 1
POLS = 0
POLS = 1
POLS = 0
POLS = 1
POLS = 0
POLS = 1
POLS = 0
t
SFSPE
Figure 17. PPI GP Rx Mode with External Frame Sync Timing (Bit 4 of PLL_CTL Set)
DATA
SAMPLING/
FRAME
SYNC
SAMPLING
EDGE
Figure 16. PPI GP Tx Mode with External Frame Sync Timing (Default)
t
SFSPE
t
HFSPE
FRAME
SYNC IS
SAMPLED
Rev. B | Page 30 of 64 | June 2007
t
HFSPE
t
SDRPE
DATA
SAMPLING/
FRAME
SYNC
SAMPLING
EDGE
DATA0 IS
DRIVEN
OUT
t
t
HDTPE
HDRPE
t
DDTPE
DATA0

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