ADSP-BF561SBBCZ-5A2 AD [Analog Devices], ADSP-BF561SBBCZ-5A2 Datasheet - Page 22

• Manufacturer Part Number: ADSP-BF561SBBCZ-5A2
• Manufacturer: AD [Analog Devices]

ADSP-BF561
TIMING SPECIFICATIONS
Table 11
the ADSP-BF561 clocks (t
MSEL, SSEL, and CSEL ratios so as not to exceed the maximum
core clock, system clock, and Voltage Controlled Oscillator
Table 11. Core Clock (CCLK) Requirements—500 MHz and 533 MHz Speed Grade Models
1
2
3
4
Table 12. Core Clock (CCLK) Requirements—600 MHz Speed Grade Models in CSP_BGA Package
1
Table 13. Core Clock (CCLK) Requirements—600 MHz Speed Grade Models in PBGA Package
1
2
Table 14. Phase-Locked Loop Operating Conditions
Table 15. System Clock (SCLK) Requirements
1
Parameter
f
f
f
f
f
f
Parameter
f
f
f
f
f
Parameter
f
f
f
f
f
f
Parameter
Voltage Controlled Oscillator (VCO) Frequency
Parameter
f
f
See
External Voltage regulation is required on automotive grade models (see
Not applicable to nonautomotive grade models. See
Not applicable to automotive grade models in PBGA package. See
See
See
External voltage regulator required to ensure proper operation at 600 MHz 1.35 V nominal.
t
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
SCLK
SCLK
SCLK
Ordering Guide on Page
Ordering Guide on Page
Ordering Guide on Page
(= 1/f
SCLK
CCLK Frequency (V
CCLK Frequency (V
CCLK Frequency (V
CCLK Frequency (V
CCLK Frequency (V
CCLK Frequency (V
CCLK Frequency (V
CCLK Frequency (V
CCLK Frequency (V
CCLK Frequency (V
CCLK Frequency (V
CCLK Frequency (V
CCLK Frequency (V
CCLK Frequency (V
CCLK Frequency (V
CCLK Frequency (V
CCLK Frequency (V
through
) must be greater than or equal to t
1
Table 13
64.
64.
64.
CCLK
CLKOUT/SCLK Frequency (V
CLKOUT/SCLK Frequency (V
describe the timing requirements for
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
= 1/f
= 1.2825 V minimum)
= 1.1875 V minimum)
= 1.045 V minimum)
= 0.95 V minimum)
= 0.855 V minimum)
= 0.8 V minimum)
= 1.25 Vminimum)
= 1.1875 Vminimum)
= 1.045 Vminimum)
= 0.95 Vminimum)
= 0.855 Vminimum)
= 0.8 V minimum)
= 1.1875 V minimum)
= 1.045 V minimum)
= 0.95 V minimum)
= 0.855 V minimum)
= 0.8 V minimum)
CCLK
CCLK
). Take care in selecting
.
Ordering Guide on Page
4
2, 3
3, 4
Rev. B | Page 22 of 64 | June 2007
2
Ordering Guide on Page
DDINT
DDINT
≥ 1.14 V)
< 1.14 V)
Ordering Guide on Page
64.
(VCO) operating frequencies, as described in
mum Ratings on Page
operating conditions.
64.
64) to ensure correct operation.
Min
50
1
21.
1
Table 14
Max V
133
100
1
describes phase-locked loop
DDEXT
= 2.5 V/3.3 V
Max
Maximum f
Max
533
500
444
350
300
250
Max
600
475
425
375
250
Max
600
500
444
350
300
250
Absolute Maxi-
CCLK
Unit
MHz
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
Unit
Unit
MHz
MHz
MHz
MHz
MHz
MHz