ADSP-BF561SBBCZ-5A2 AD [Analog Devices], ADSP-BF561SBBCZ-5A2 Datasheet - Page 34
ADSP-BF561SBBCZ-5A2
Manufacturer Part Number
ADSP-BF561SBBCZ-5A2
Description
Manufacturer
AD [Analog Devices]
Datasheet
1.ADSP-BF561SBBCZ-5A2.pdf
(64 pages)
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ADSP-BF561
Table 24. Serial Ports—Enable and Three-State
1
Table 25. External Late Frame Sync
1
2
Parameter
Switching Characteristics
t
t
t
t
Parameter
Switching Characteristics
t
t
Referenced to drive edge.
MCE = 1, TFSx enable and TFSx valid follow t
If external RFSx/TFSx setup to RSCLKx/TSCLKx > t
DTENE
DDTTE
DTENI
DDTTI
DDTLFSE
DTENLFS
Data Delay from Late External TFSx or External RFSx with MCE = 1, MFD = 0
Data Enable from Late FS or MCE = 1, MFD = 0
Data Enable Delay from External TSCLKx
Data Disable Delay from External TSCLKx
Data Enable Delay from Internal TSCLKx
Data Disable Delay from Internal TSCLKx
EXTERNAL RFS WITH MCE = 1, MFD = 0
LATE EXTERNAL TFS
RSCLKx
RFSx
DTx
TSCLKx
DTx
TFSx
DTENLFS
and t
DRIVE
SCLKE
DRIVE
/2, then t
DDTLFSE
t
t
DTENLFS
t
DTENLFS
t
DDTLFSE
DDTLFSE
t
1
1
SFSE/I
1
.
t
1
SFSE/I
Rev. B | Page 34 of 64 | June 2007
1, 2
DDTTE
Figure 20. External Late Frame Sync
/
SAMPLE
I
SAMPLE
and t
1ST BIT
1ST BIT
DTENE
/
I
apply; otherwise t
DRIVE
DRIVE
t
t
HOFSE/I
DTENE/I
t
t
HOFSE/I
DTENE/I
t
DDTTE/I
t
DDTTE/I
DDTLFSE
1, 2
and t
DTENLFS
Min
0
–2.0
apply.
2ND BIT
2ND BIT
Min
0
Max
10.0
3.0
Max
10.0
Unit
ns
ns
ns
ns
Unit
ns
ns
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