PIC18F23K20-E/MLQTP MICROCHIP [Microchip Technology], PIC18F23K20-E/MLQTP Datasheet - Page 102

• Manufacturer Part Number: PIC18F23K20-E/MLQTP
• Description: 28/40/44-Pin Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F2XK20/4XK20
7.6
Data EEPROM memory has its own code-protect bits in
Configuration
operations are disabled if code protection is enabled.
The microcontroller itself can both read and write to the
internal data EEPROM, regardless of the state of the
code-protect Configuration bit. Refer to Section 23.0
“Special Features of the CPU” for additional
information.
7.7
There are conditions when the user may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been implemented. On power-up, the WREN bit is
cleared. In addition, writes to the EEPROM are blocked
during
parameter 33).
EXAMPLE 7-3:
TABLE 7-1:
DS41303B-page 100
INTCON
EEADR
EEADRH
EEDATA
EECON2
EECON1
IPR2
PIR2
PIE2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.
Loop
Name
Operation During Code-Protect
Protection Against Spurious Write
the
CLRF
BCF
BCF
BCF
BSF
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BTFSC
BRA
INCFSZ
BRA
BCF
BSF
EEPROM Data Register
EEPROM Control Register 2 (not a physical register)
GIE/GIEH
EEADR7
Power-up
OSCFIP
OSCFIF
OSCFIE
Words.
EEPGD
Bit 7
—
REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY
EEADR
EECON1, CFGS
EECON1, EEPGD
INTCON, GIE
EECON1, WREN
EECON1, RD
55h
EECON2
0AAh
EECON2
EECON1, WR
EECON1, WR
$-2
EEADR, F
LOOP
EECON1, WREN
INTCON, GIE
DATA EEPROM REFRESH ROUTINE
External
PEIE/GIEL
Timer
EEADR6
CFGS
Bit 6
C1IP
C1IF
C1IE
—
read
period
EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0
TMR0IE
Bit 5
C2IP
C2IF
C2IE
and
Advance Information
—
—
(T
; Start at address 0
; Set for memory
; Set for Data EEPROM
; Disable interrupts
; Enable writes
; Loop to refresh array
; Read current address
;
; Write 55h
;
; Write 0AAh
; Set WR bit to begin write
; Wait for write to complete
; Increment address
; Not zero, do it again
; Disable writes
; Enable interrupts
PWRT
write
INT0IE
FREE
,
EEIP
EEIF
EEIE
Bit 4
—
WRERR
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch or software malfunction.
7.8
The data EEPROM is a high-endurance, byte
addressable array that has been optimized for the
storage of frequently changing information (e.g.,
program variables or other data that are updated often).
When variables in one section change frequently, while
variables in another section do not change, it is possible
to exceed the total number of write cycles to the
EEPROM (specification D124) without exceeding the
total number of write cycles to a single byte (specification
D120). If this is the case, then an array refresh must be
performed. For this reason, variables that change
infrequently (such as constants, IDs, calibration, etc.)
should be stored in Flash program memory.
BCLIP
BCLIF
BCLIE
RBIE
Bit 3
—
Using the Data EEPROM
TMR0IF
HLVDIP
HLVDIE
HLVDIF
WREN
Bit 2
—
EEADR9 EEADR8
TMR3IP
TMR3IF
TMR3IE
INT0IF
© 2007 Microchip Technology Inc.
Bit 1
WR
CCP2IP
CCP2IF
CCP2IE
RBIF
Bit 0
RD
on page
Values
Reset
57
59
59
59
59
59
60
60
60