PIC18F23K20-E/MLQTP MICROCHIP [Microchip Technology], PIC18F23K20-E/MLQTP Datasheet - Page 187

• Manufacturer Part Number: PIC18F23K20-E/MLQTP
• Description: 28/40/44-Pin Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

17.0
17.1
The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I
The I
hardware:
• Master mode
• Multi-Master mode
• Slave mode
17.2
The MSSP module has seven associated registers.
These include:
• SSPSTA – STATUS register
• SSPCON1 – First Control register
• SSPCON2 – Second Control register
• SSPBUF – Transmit/Receive buffer
• SSPSR – Shift register (not directly accessible)
• SSPADD – Address register
• SSPMSK – Address Mask register
The use of these registers and their individual Configu-
ration bits differ significantly depending on whether the
MSSP module is operated in SPI or I
Additional details are provided under the individual
sections.
© 2007 Microchip Technology Inc.
- Full Master mode
- Slave mode (with general address call)
2
C interface supports the following modes in
MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
Master SSP (MSSP) Module
Overview
Control Registers
2
C)
2
C mode.
Advance Information
17.3
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four
modes
communication, typically three pins are used:
• Serial Data Out – SDO
• Serial Data In – SDI/SDA
• Serial Clock – SCK/SCL
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select – SS
Figure 17-1 shows the block diagram of the MSSP
module when operating in SPI mode.
FIGURE 17-1:
PIC18F2XK20/4XK20
SCK/SCL
SDI/SDA
SDO
SS
SPI Mode
of
SPI
Read
are
SS Control
Select
SMP:CKE
Edge
MSSP BLOCK DIAGRAM
(SPI MODE)
Select
bit 0
Edge
Enable
supported.
TRIS bit
SSPBUF Reg
Data to TX/RX in SSPSR
SSPSR Reg
2
Clock Select
SSPM<3:0>
4
DS41303B-page 185
2
To
(
Prescaler
4, 16, 64
TMR2 Output
Write
Clock
Shift
accomplish
Data Bus
Internal
2
T
OSC
)