PIC18F258 MICROCHIP [Microchip Technology], PIC18F258 Datasheet - Page 231

• Manufacturer Part Number: PIC18F258
• Description: High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN
• Manufacturer: MICROCHIP [Microchip Technology]

19.7
All nodes on a given CAN bus must have the same
nominal bit rate. The CAN protocol uses Non-Return-
to-Zero (NRZ) coding, which does not encode a clock
within the data stream. Therefore, the receive clock
must be recovered by the receiving nodes and
synchronized to the transmitters clock.
As oscillators and transmission time may vary from
node to node; the receiver must have some type of
Phase Lock Loop (PLL) synchronized to data transmis-
sion edges to synchronize and maintain the receiver
clock. Since the data is NRZ coded, it is necessary to
include bit stuffing to ensure that an edge occurs at
least every six bit times, to maintain the Digital Phase
Lock Loop (DPLL) synchronization.
The bit timing of the PIC18FXX8 is implemented using
a DPLL that is configured to synchronize to the incom-
ing data, and provides the nominal timing for the trans-
mitted data. The DPLL breaks each bit time into
multiple segments, made up of minimal periods of time
called the Time Quanta (T
Bus timing functions executed within the bit time frame,
such as synchronization to the local oscillator, network
transmission delay compensation, and sample point
positioning, are defined by the programmable bit timing
logic of the DPLL.
All devices on the CAN bus must use the same bit rate.
However, all devices are not required to have the same
master oscillator clock frequency. For the different clock
frequencies of the individual devices, the bit rate has to
be adjusted by appropriately setting the baud rate
prescaler and number of time quanta in each segment.
The Nominal Bit Rate is the number of bits transmitted
per second, assuming an ideal transmitter with an ideal
oscillator, in the absence of resynchronization. The
nominal bit rate is defined to be a maximum of 1 Mb/s.
FIGURE 19-7:
 2002 Microchip Technology Inc.
Input
Signal
Bit
Time
Intervals
T
Q
Baud Rate Setting
Segment
Sync
BIT TIME PARTITIONING
Q
).
Propagation
Segment
Preliminary
Nominal Bit Time
Segment 1
Phase
The Nominal Bit Time is defined as
The Nominal Bit Time can be thought of as being
divided into separate, non-overlapping time segments.
These segments (Figure 19-7) include:
• Synchronization Segment (Sync_Seg)
• Propagation Time Segment (Prop_Seg)
• Phase Buffer Segment 1 (Phase_Seg1)
• Phase Buffer Segment 2 (Phase_Seg2)
The time segments (and thus the Nominal Bit Time) are
in turn made up of integer units of time called Time
Quanta or T
inal bit time is programmable from a minimum of 8 T
to a maximum of 25 T
mum Nominal Bit Time is 1 µs, corresponding to a max-
imum 1 Mb/s rate. The actual duration is given by the
relationship
The Time Quantum is a fixed unit derived from the
oscillator period. It is also defined by the programmable
baud rate prescaler with integer values from 1 to 64, in
addition to a fixed divide-by-two for clock generation.
Mathematically, this is
where F
sponding oscillator period, and BRP is an integer (0
through 63) represented by the binary values of
BRGCON1<5:0>.
Nominal Bit Time = T
Sample Point
OSC
T
T
Q
Q
Q
(µs) = (2 * (BRP+1)) / F
Phase_Seg1 + Phase_Seg2)
(µs) = (2 * (BRP+1)) * T
is the clock frequency, T
(see Figure 19-7). By definition, the nom-
T
BIT
= 1 / Nominal Bit rate
Q
Q
. Also, by definition, the mini-
Segment 2
PIC18FXX8
* (Sync_Seg + Prop_Seg +
or
Phase
OSC
DS41159B-page 229
OSC
OSC
(MHz)
(µs)
is the corre-
Q