PIC18F258 MICROCHIP [Microchip Technology], PIC18F258 Datasheet - Page 245

• Manufacturer Part Number: PIC18F258
• Description: High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN
• Manufacturer: MICROCHIP [Microchip Technology]

20.4
Figure 20-3 shows the operation of the A/D converter
after the GO bit has been set. Clearing the GO/DONE
bit during a conversion will abort the current conver-
sion. The A/D result register pair will NOT be updated
with the partially completed A/D conversion sample.
That is, the ADRESH:ADRESL registers will continue
to contain the value of the last completed conversion
(or the last value written to the ADRESH:ADRESL reg-
isters). After the A/D conversion is aborted, a 2 T
is required before the next acquisition is started. After
this 2 T
automatically started.
FIGURE 20-3:
TABLE 20-3:
 2002 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
ADRESH A/D Result Register
ADRESL
ADCON0
ADCON1
PORTA
TRISA
PORTE
LATE
TRISE
Legend: x = unknown, u = unchanged, - = unimplemented, read as ’0’. Shaded cells are not used for A/D conversion.
Note 1: These bits are reserved on PIC18F2X8 devices; always maintain these bits clear.
Name
Note:
AD
A/D Conversions
GIE/GIEH PEIE/GIEL
PSPIE
PSPIP
A/D Result Register
wait, acquisition on the selected channel is
PSPIF
ADCS1
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
ADFM
T
Bit 7
IBF
CY
Set GO bit
—
—
—
—
—
—
—
Holding capacitor is disconnected from analog input
(typically 100 ns)
- T
(1)
(1)
(1)
SUMMARY OF A/D REGISTERS
AD
PORTA Data Direction Register
Conversion Starts
CMIF
CMIE
CMIP
T
ADCS0
ADCS2
A/D CONVERSION T
ADIE
ADIP
ADIF
AD
b9
Bit 6
OBF
RA6
—
—
1 T
(1)
(1)
(1)
AD
b8
TMR0IE
2 T
CHS2
RCIF
RCIE
RCIP
IBOV
Bit 5
RA5
—
—
—
—
—
—
AD
b7
Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared,
3 T
PSPMODE
INT0IE
AD
b6
CHS1
Bit 4
TXIF
TXIE
TXIP
EEIF
EEIE
EEIP
RA4
—
—
—
4 T
AD
AD
ADIF bit is set, holding capacitor is connected to analog input.
AD
CYCLES
b5
wait
Preliminary
5 T
PCFG3
SSPIE
SSPIP
SSPIF
BCLIF
BCLIE
BCLIP
CHS0
Bit 3
RBIE
RA3
—
—
—
AD
b4
6 T
GO/DONE
TMR0IF
CCP1IE
CCP1IP
TRISE2
CCP1IF
PCFG2
LATE2
LVDIE
LVDIP
LVDIF
20.5
An A/D conversion can be started by the “special event
trigger” of the ECCP module. This requires that the
ECCP1M3:ECCP1M0 bits (ECCP1CON<3:0>) be pro-
grammed as 1011 and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D conversion and
the Timer1 (or Timer3) counter will be reset to zero.
Timer1 (or Timer3) is reset to automatically repeat the
A/D acquisition period with minimal software overhead
(moving ADRESH/ADRESL to the desired location). The
appropriate analog input channel must be selected and
the minimum acquisition done before the “special event
trigger” sets the GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared), the
“special event trigger” will be ignored by the A/D module,
but will still reset the Timer1 (or Timer3) counter.
Bit 2
AD
b3
RA2
RE2
7 T
AD
b2
TMR3IE ECCP1IE
TMR3IP ECCP1IP
TMR3IF ECCP1IF
TRISE1
Use of the ECCP Trigger
TMR2IF
TMR2IE
TMR2IP
PCFG1
8
INT0IF
LATE1
Bit 1
RA1
RE1
—
T
AD
b1
9 T
AD
TMR1IF
TMR1IE
TMR1IP
TRISE0
PCFG0
LATE0
b0
ADON
RBIF
Bit 0
RA0
RE0
10
PIC18FXX8
T
AD
(1)
(1)
(1)
b0
11
0000 000x 0000 000u
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
-0-0 0000 -0-0 0000
-0-0 0000 -0-0 0000
-0-0 0000 -0-0 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 00-0 0000 00-0
00-- 0000 00-- 0000
-00x 0000 -00u 0000
-111 1111 -111 1111
---- -000 ---- -000
---- -xxx ---- -uuu
0000 -111 0000 -111
POR, BOR
Value on
DS41159B-page 243
Value on
RESETS
all other