PEB20571 INFINEON [Infineon Technologies AG], PEB20571 Datasheet - Page 209

• Manufacturer Part Number: PEB20571
• Description: ICs for Communications
• Manufacturer: INFINEON [Infineon Technologies AG]

6.2.11.10 PFS Sync Register
PFS Sync Register (CPFSSY)
Reset value: 0000
Note: ’x’ = unused bits, read as 0.
During read cycle the 2 LSBs are driven by the the PFS-sync state-machine's state bits.
This is needed only for testing.
The PFS-sync Signal actually resets the 61.44 MHz-Clock-division-Chain. The PFS-
sync signal activated with the PFS-rising edge detection, but only when the internal-reset
is activated or after a "PFS-sync" instruction was carried out by the OAK. The goal of
reseting the 61.44MHz-Clock-division-Chain by PFS-sync, is to lead to a situation in
which FSC rises with PFS. After the initial reset by the PFS-sync a small- and flexible
phase difference is maintained by the DCXO-PLL. A write access to PFS-Sync Register,
resets the 61MHz clock-division chain, including FSC, by the next PFS rising-edge
detection. This is true only if the write access was carried-out before the falling edge of
PFS. If the write-access comes after the falling edge of PFS, the acctuall sync operation
will not be carried out by the next PFS rising-edge, but with one that will come after it.
The written value does not make any difference.
6.2.11.11 Realtime Counter Register
RT Counter Register (CRTCNT)
Reset value: 0000
This 18-bit counter counts 8 kHz cycles. It is used by the software to time the handling
of required tasks. One period of the counter (counting from 0000H to FFFFH and back
Preliminary Data Sheet
15
15
7
7
x
x
H
H
14
14
6
6
x
x
13
13
x
5
x
5
RTCOUNT(15:8)
RTCOUNT(7:0)
12
12
x
4
x
4
read/write
read
6-69
11
11
3
3
x
10
10
2
2
x
Register Description
PFSSYNC(1:0)
Address: D089
Address: D08E
9
1
9
1
x
DELIC
2003-08
8
x
0
8
0
H
H