LAN9218I_07 SMSC [SMSC Corporation], LAN9218I_07 Datasheet
LAN9218I_07
Related parts for LAN9218I_07
LAN9218I_07 Summary of contents
Page 1
PRODUCT FEATURES Highlights Optimized for the highest performance applications Efficient architecture with low CPU overhead Easily interfaces to most 32-bit and 16-bit embedded CPU’s Integrated PHY with HP Auto-MDIX Supports audio & video streaming over Ethernet: multiple high-definition (HD) MPEG2 ...
Page 2
LAN9218i-MT FOR 100-PIN, TQFP LEAD-FREE ROHS COMPLIANT PACKAGE WITH E3 FINISH (MATTE TIN) 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2007 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating ...
Page 3
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet Table of Contents Chapter 1 General Description . . . . . . . . . . . . . . . . . . . . ...
Page 4
TX Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 5
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet 5.3.5 BYTE_TEST—Byte Order Test Register ...
Page 6
RX Data FIFO Direct PIO Burst Reads ...
Page 7
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet List of Figures Figure 1.1 System Block Diagram ...
Page 8
List of Tables Table 2.1 Host Bus Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 9
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet Chapter 1 General Description The LAN9218i is a full-featured, single-chip 10/100 Ethernet controller designed for embedded applications where performance, flexibility, ease of integration and system cost control ...
Page 10
System Memory Microprocessor/ System Bus Microcontroller The SMSC LAN9218i integrated 10/100 MAC/PHY controller is a peripheral chip that performs the function of translating parallel data from a host controller into Ethernet packets. The LAN9218i Ethernet MAC/PHY controller is designed ...
Page 11
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet 1.2 Internal Block Overview This section provides an overview of each of these functional blocks as shown in Block Diagram". PME Wakup Indicator Power Management Host Bus ...
Page 12
The MAC Interface Layer (MIL), within the MAC, contains a 2K Byte transmit and a 128 Byte receive FIFO which is separate from the TX and RX FIFOs. The FIFOs within the MAC are not directly accessible from the host ...
Page 13
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet 1.11 Host Bus Interface (SRAM Interface) The host bus interface provides a FIFO interface for the transmit and receive data paths, as well as an interface for ...
Page 14
Chapter 2 Pin Description and Configuration FIFO_SEL 76 VSS_A 77 (Note 1) TPO- 78 (Note 1) TPO+ 79 VSS_A 80 VDD_A 81 (Note 1) TPI - 82 (Note 1) TPI VDD_A 85 VSS_A 86 EXRES1 87 VSS_A ...
Page 15
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet PIN NO. NAME 21-26,29- Host Data High 33,36-40 43-46,49- Host DataLow 53,56-59,62- 64 12-18 Host Address 92 Read Strobe 93 Write Strobe 94 Chip Select 72 Interrupt ...
Page 16
PIN NO. NAME 79 TPO+ 78 TPO- 83 TPI+ 82 TPI- 87 PHY External Bias Resistor Note: The pin names for the twisted pair pins shown above apply to a normal connection Auto- MDIX is enabled and a ...
Page 17
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet Table 2.4 Serial EEPROM Interface Signals (continued) PIN NO. NAME 69 EEPROM Clock, EECLK/GPO4/ GPO4 RX_DV, RX_DV/RX_CLK RX_CLK PIN NO. NAME 6 Crystal 1, Clock In XTAL1/CLKIN ...
Page 18
Table 2.5 System and Power Signals (continued) PIN NO. NAME 70 Wakeup Indicator 73 Auto-MDIX Enable AMDIX_EN 74 10/100 Selector SPEED_SEL 71,84, No Connect 90,91 75 Pull-Down (Reserved) Revision 1.8 (06-06-07) High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and ...
Page 19
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet Table 2.5 System and Power Signals (continued) PIN NO. NAME 100, General Purpose 99,98 I/O data, nLED1 (Speed Indicator), nLED2 (Link & Activity Indicator), nLED3 (Full- Duplex ...
Page 20
Table 2.5 System and Power Signals (continued) PIN NO. NAME 3,65 Core Voltage VDD_CORE Decoupling 1,66 Core Ground GND_CORE 7 PLL Power 4 PLL Ground 8 Reference Power 11 Reference Ground Note 2.1 Please refer to the SMSC application note ...
Page 21
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet TYPE Analog bi-directional AIO Crystal oscillator input pin ICLK Crystal oscillator output pin OCLK LAN9218i SMSC Table 2.6 Buffer Types DESCRIPTION 21 DATASHEET Revision 1.8 (06-06-07) ...
Page 22
Chapter 3 Functional Description 3.1 10/100 Ethernet MAC The Ethernet Media Access controller (MAC) incorporates the essential protocol requirements for operating an Ethernet/IEEE 802.3-compliant node and provides an interface between the host subsystem and the internal Ethernet PHY. The MAC ...
Page 23
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet 3.2 Flow Control The LAN9218i Ethernet MAC supports full-duplex flow control using the pause operation and control frame. It also supports half-duplex flow control using back pressure. ...
Page 24
Address Filtering Functional Description The Ethernet address fields of an Ethernet Packet, consists of two 6-byte fields: one for the destination address and one for the source address. The first bit of the destination address signifies whether it is ...
Page 25
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet Table 3.1 Address Filtering Modes (continued) MCPAS PRMS INVFILT 3.4 Filtering Modes 3.4.1 Perfect Filtering This filtering ...
Page 26
Wake-up Frame Detection Setting the Wake-Up Frame Enable bit (WUEN) in the “WUCSR—Wake-up Control and Status Register”, places the LAN9218i MAC in the wake-up frame detection mode. In this mode, normal data reception is disabled, and detection logic within ...
Page 27
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet Table 3.3 Filter i Byte Mask Bit Definitions FIELD DESCRIPTION 31 Must be zero (0) 30:0 Byte Mask: If bit j of the byte mask is set, ...
Page 28
Magic Packet Detection Setting the Magic Packet Enable bit (MPEN) in the “WUCSR—Wake-up Control and Status Register”, places the LAN9218i MAC in the “Magic Packet” detection mode. In this mode, normal data reception is disabled, and detection logic within ...
Page 29
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet 3.6.2 16-bit Bus Writes The host processor is required to perform two contiguous 16-bit writes to complete a single DWORD transfer. This DWORD must begin and end ...
Page 30
General Purpose Timer (GP Timer) The General Purpose Timer is a programmable block that can be used to generate periodic host interrupts. The resolution of this timer is 100uS. The GP Timer loads the GPT_CNT Register with the value ...
Page 31
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet If the EEPROM operation is the “write location” (WRITE) or “write all” (WRAL) commands, the host must first write the desired data into the E2P_DATA register. The ...
Page 32
Supported EEPROM Operations The EEPROM controller supports the following EEPROM operations under host control via the E2P_CMD register. The operations are commonly supported by “93C46” EEPROM devices. A description and functional timing diagram is provided below for each operation. ...
Page 33
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet EWDS (Erase/Write Disable): After issued, the EEPROM will ignore erase and write commands. To re-enable erase/write operations issue the EWEN command. EECS EECLK EEDIO (OUTPUT) EEDIO (INPUT) ...
Page 34
READ (Read Location): This command will cause a read of the EEPROM location pointed to by EPC Address (EPC_ADDR). The result of the read is available in the E2P_DATA register. EECS EECLK EEDIO (OUTPUT) 1 EEDIO (INPUT) WRITE (Write Location): ...
Page 35
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet WRAL (Write All): If erase/write operations are enabled in the EEPROM, this command will cause the contents of the E2P_DATA register to be written to every EEPROM ...
Page 36
Power Management The LAN9218i supports power-down modes to allow applications to minimize power consumption. The following sections describe these modes. 3.9.1 System Description Power is reduced to various modules by disabling the clocks as outlined in Table 3.9, “Power ...
Page 37
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet noted above, the host is required to check the READY bit and verify that it is set before attempting any other reads or writes of the device. ...
Page 38
Power Management Event Indicators Figure 3. simplified block diagram of the logic that controls the external PME, and internal pme_interrupt signals. The pme_interrupt signal is used to set the PME_INT status bit in the INT_STS register, which, ...
Page 39
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet 3.9.3.2 Energy Detect Power-Down This power-down mode is activated by setting the Phy register bit 17. Please refer to 5.5.8, "Mode Control/Status," on page 110 ...
Page 40
Power-On Reset (POR) A Power-On reset occurs whenever power is initially applied to the LAN9218i power is removed and reapplied to the LAN9218i. A timer within the LAN9218i will assert the internal reset for approximately 22ms. The ...
Page 41
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet 3.10.5.2 PHY Soft Reset via PHY Basic Control Register (PHY Reg. 0.15) The PHY Reg. 0.15 Soft Reset is initiated by writing a ‘1’ to bit 15 ...
Page 42
Last Buffer in Packet Figure 3.11 Simplified Host TX Flow Diagram 3.11.1 TX Buffer Format TX buffers exist in the host’s memory in a given format. The host writes a TX command word into the TX data buffer before moving ...
Page 43
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet Host Write Figure 3.12, "TX Buffer noted that not all of the data shown in this diagram is actually stored in the TX data FIFO. This must ...
Page 44
TX COMMAND ‘A’ BITS 31 Interrupt on Completion. When set, the TXDONE flag will be asserted when the current buffer has been fully loaded into the TX FIFO. This flag may be optionally mapped to a host interrupt. 30:26 Reserved. ...
Page 45
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet TX COMMAND ‘B’ BITS 31:16 Packet Tag. The host should write a unique packet identifier to this field. This identifier is added to the corresponding TX status ...
Page 46
Additionally, The LAN9218i has specific rules regarding the use of transmit buffers when in Store-and- Forward mode (i.e., HW_CFG[SF] = 1). When this mode is enabled, the total space consumed in the TX FIFO (MIL) must be limited to no ...
Page 47
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet BITS 8 Excessive Collisions. When set, this bit indicates that the transmission was aborted after 16 collisions while attempting to transmit the current packet. 7 Reserved. This ...
Page 48
Buffer 2: 10-Byte “Data Start Offset” 17-Bytes of payload data 16-Byte “Buffer End Alignment” Revision 1.8 (06-06-07) High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support 48 DATASHEET Datasheet LAN9218i SMSC ...
Page 49
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet Figure 3.13, "TX Example 1" how data is passed to the TX data FIFO. Data W ritten to the Ethernet Controller 31 TX Com m and 'A' ...
Page 50
TX Example 2 In this example, a single 183-Byte Ethernet packet will be transmitted. This packet single buffer as follows: 2-Byte “Data Start Offset” 183-Bytes of payload data 4-Byte “Buffer End Alignment” Figure 3.14, "TX Example ...
Page 51
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet 3.11.7 TX Data FIFO Underrun If the MIL is not operating in store and forward mode, and the host is unable supply data at the Ethernet line ...
Page 52
The host must use caution when reading the RX data and status. The host must never read more data than what is available in the FIFOs. If this is attempted an underrun condition will occur. If this error occurs, the ...
Page 53
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet Last Packet Figure 3.15 Host Receive Routine Using Interrupts Last Packet Figure 3.16 Host Receive Routine with Polling 3.12.1.1 Receive Data FIFO Fast Forward The RX data ...
Page 54
When performing a fast-forward, there must be at least 4 DWORDs of data in the RX data FIFO for the packet being discarded. For less than 4 DWORDs do not use RX_FFWD. In this case data must be read from ...
Page 55
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet 3.12.2 RX Packet Format The RX status words can be read from the RX status FIFO port, while the RX data packets can be read from the ...
Page 56
BITS 11 Runt Frame. When set, this bit indicates that frame was prematurely terminated before the collision window (64 bytes). Runt frames are passed on to the host only if the Pass Bad Frames bit MAC_CR Bit [16] is set. ...
Page 57
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet Chapter 4 Internal Ethernet PHY 4.1 Top Level Functional Description Functionally, the internal PHY can be divided into the following sections: 100Base-TX transmit and receive 10Base-T transmit ...
Page 58
CODE GROUP SYM 11110 0 0 01001 1 1 10100 2 2 10101 3 3 01010 4 4 01011 5 5 01110 6 6 01111 7 7 10010 8 8 10011 9 9 10110 A A 10111 B B 11010 ...
Page 59
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet CODE GROUP SYM 01000 V INVALID, RX_ER if during RX_DV 01100 V INVALID, RX_ER if during RX_DV 10000 V INVALID, RX_ER if during RX_DV 4.2.2 Scrambling Repeated ...
Page 60
RX_CLK MAC Internal MII 25MHz by 4 bits MLT-3 NRZI NRZI Converter Converter A/D Magnetics MLT-3 Converter 4.3 100Base-TX Receive The receive data path is shown in 4.3.1 100M Receive Input The MLT-3 from the cable is fed into the ...
Page 61
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet 4.3.4 Descrambling The descrambler performs an inverse function to the scrambler in the transmitter and also performs the Serial In Parallel Out (SIPO) conversion of the data. ...
Page 62
TX10M block outputs Normal Link Pulses (NLPs) to maintain communications with the remote link partner. 4.4.3 10M Transmit Drivers The Manchester encoded data is sent to the analog transmitter where it is shaped and filtered before ...
Page 63
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet Once auto-negotiation has completed, information about the resolved link can be passed back to the controller via the internal Serial Management Interface (SMI). The results of the ...
Page 64
Auto-negotiation can also be disabled via software by clearing register 0, bit 12. The LAN9218i does not support “Next Page" capability. 4.7 Parallel Detection If the LAN9218i is connected to a device lacking the ability to ...
Page 65
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet MODE SPEED Manual 10 Mbps Manual 10 Mbps Manual 10 Mbps Manual 10 Mbps Manual 100 Mbps Manual 100 Mbps Manual 100 Mbps Manual 100 Mbps Auto-Negotiation ...
Page 66
The figure below shows the signal names at the RJ-45 connector, The mapping of these signals to the pins on the LAN9218i is as follows: TXP = TPO+ TXN = TPO- RXP = TPI+ RXN = TPI- Figure 4.3 Direct ...
Page 67
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet Chapter 5 Register Description The following section describes all LAN9218i registers and data ports. FCh B4h B0h ACh A8h A4h A0h 50h 4Ch 48h 44h 40h 3Ch ...
Page 68
Register Nomenclature and Access Attributes SYMBOL RO Read Only register is read only, writes to this register have no effect. WO Write Only register is write only, reads always return 0. R/W Read/Write: A register ...
Page 69
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet 5.3 System Control and Status Registers Table 5.1, "Direct Address Register bus. BASE ADDRESS + OFFSET SYMBOL 50h ID_REV 54h IRQ_CFG 58h INT_STS 5Ch INT_EN 60h RESERVED ...
Page 70
ID_REV—Chip ID and Revision Offset: This register contains the ID and Revision fields for this design. BITS 31-16 Chip ID. This read-only field identifies this design 15-0 Chip Revision 5.3.2 IRQ_CFG—Interrupt Configuration Register Offset: This register configures and indicates ...
Page 71
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet BITS 4 IRQ Polarity (IRQ_POL) – When cleared, enables the IRQ line to function as an active low output. When set, the IRQ output is active high. ...
Page 72
INT_STS—Interrupt Status Register Offset: This register contains the current status of the generated interrupts. Writing the corresponding bits acknowledges and clears the interrupt. BITS 31 Software Interrupt (SW_INT). This interrupt is generated when the SW_INT_EN bit ...
Page 73
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet BITS 12 Reserved 11 TX Data FIFO Underrun Interrupt (TDFU). Generated when the TX data FIFO underruns Data FIFO Overrun Interrupt (TDFO). Generated when the ...
Page 74
INT_EN—Interrupt Enable Register Offset: This register contains the interrupt masks for IRQ. Writing 1 to any of the bits enables the corresponding interrupt as a source for IRQ. Bits in the INT_STS register will still reflect the status of ...
Page 75
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet 5.3.5 BYTE_TEST—Byte Order Test Register Offset: This register can be used to determine the byte ordering of the current configuration BITS 31:0 Byte Test 5.3.6 FIFO_INT—FIFO Level ...
Page 76
RX_CFG—Receive Configuration Register Offset: This register controls the LAN9218i receive engine. BITS 31:30 RX End Alignment. This field specifies the alignment that must be maintained on the last data transfer of a buffer. The LAN9218i will add extra DWORDs ...
Page 77
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet 5.3.8 TX_CFG—Transmit Configuration Register Offset: This register controls the transmit functions on the LAN9218i Ethernet Controller. BITS 31-16 Reserved. 15 Force TX Status Discard (TXS_DUMP). This self-clearing ...
Page 78
HW_CFG—Hardware Configuration Register Offset: Note: The transmitter and receiver must be stopped before writing to this register. Refer to 3.11.9, "Stopping and Starting the Transmitter," on page 51 Starting the Receiver," on page 56 BITS 31-25 Reserved 24 AMDIX_EN ...
Page 79
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet BITS 13-12 Threshold Control Bits (TR). These control the transmit threshold values the MIL should use. These bits are used when the SF bit is reset. The ...
Page 80
Allowable settings for Configurable FIFO Memory Allocation TX and RX FIFO space is configurable through the CSR - HW_CFG register defined above. The user must select the FIFO allocation by setting the TX FIFO Size (TX_FIF_SZ) field in the ...
Page 81
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet In addition to the host-accessible FIFOs, the MAC Interface Layer (MIL) contains an additional 2K bytes of TX, and 128 bytes of RX FIFO buffering. These sizes ...
Page 82
RX_FIFO_INF—Receive FIFO Information Register Offset: This register contains the used space in the receive FIFOs of the LAN9218i Ethernet Controller. BITS 31-24 Reserved 23-16 RX Status FIFO Used Space (RXSUSED). Indicates the amount of space in DWORDs, used in ...
Page 83
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet 5.3.13 PMT_CTRL— Power Management Control Register Offset: This register controls the Power Management features. This register can be read while the power saving mode. ...
Page 84
BITS 5-4 WAKE-UP Status (WUPS) – This field indicates the cause of a wake-up event detection as follows 00b -- No wake-up event detected 01b -- Energy detected 10b -- Wake-up frame or magic packet detected 11b -- Indicates multiple ...
Page 85
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet 5.3.14 GPIO_CFG—General Purpose IO Configuration Register Offset: This register configures the GPIO and LED functions. BITS 31 Reserved 30:28 LED[3:1] enable (LEDx_EN). A ‘1’ sets the associated ...
Page 86
BITS 2:0 GPIO Data 0-2 (GPIODn). When enabled as an output, the value written is reflected on GPIOn. When read, GPIOn reflects the current state of the corresponding GPIO pin. GPIO0 – bit 0 GPIO1 – bit 1 GPIO2 – ...
Page 87
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet 5.3.16 GPT_CNT-General Purpose Timer Current Count Register Offset: This register reflects the current value of the GP Timer. BITS 31-16 Reserved 15-0 General Purpose Timer Current Count ...
Page 88
FREE_RUN—Free-Run 25MHz Counter Offset: This register reflects the value of the free-running 25MHz counter. BITS 31:0 Free Running SCLK Counter (FR_CNT): Note: This field reflects the value of a free-running 32-bit counter. At reset the counter starts at zero ...
Page 89
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet 5.3.20 MAC_CSR_CMD – MAC CSR Synchronizer Command Register Offset: This register is used to control the read and write operations with the MAC CSR’s BITS 31 CSR ...
Page 90
AFC_CFG – Automatic Flow Control Configuration Register Offset: This register configures the mechanism that controls both the automatic, and software-initiated transmission of pause frames and back pressure. Note: The LAN9218i will not transmit pause frames or assert back pressure ...
Page 91
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet BITS 0 Flow Control on Any Frame (FCANY). When this bit is set, the LAN9218i will assert back pressure, or transmit a pause frame when the AFC ...
Page 92
E2P_CMD – EEPROM Command Register Offset: This register is used to control the read and write operations with the Serial EEPROM. BITS 31 EPC Busy: When written into this bit, the operation specified in the EPC ...
Page 93
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet BITS 30-28 EPC command. This field is used to issue commands to the EEPROM controller. The EPC will execute commands when the EPC Busy bit is set. ...
Page 94
BITS EPC Time-out EEPROM operation is performed, and there is no response from the EEPROM within 30mS, the EEPROM controller will time- out and return to its idle state. This bit is set when a time-out occurs ...
Page 95
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet 5.4 MAC Control and Status Registers These registers are located in the MAC module and are accessed indirectly through the MAC-CSR synchronizer port. Table 5.6, "MAC CSR ...
Page 96
MAC_CR—MAC Control Register Offset: Default Value: This register establishes the RX and TX operation modes and controls for address filtering and packet filtering. BITS 31 Receive All Mode (RXALL). When set, all incoming packets will be received and passed ...
Page 97
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet BITS 13 Hash/Perfect Filtering Mode (HPFILT). When reset (0), the LAN9218i will implement a perfect address filter on incoming frames according the address specified in the MAC ...
Page 98
BITS 5 Deferral Check (DFCHK). When set, enables the deferral check in the MAC. The MAC will abort the transmission attempt if it has deferred for more than 24,288 bit times. Deferral starts when the transmitter is ready to transmit, ...
Page 99
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet 5.4.3 ADDRL—MAC Address Low Register Offset: Default Value: The MAC Address Low register contains the lower 32 bits of the physical address of the MAC. The contents ...
Page 100
HASHH—Multicast Hash Table High Register Offset: Default Value: The 64-bit Multicast table is used for group address filtering. For hash filtering, the contents of the destination address in the incoming frame is used to index the contents of the ...
Page 101
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet 5.4.6 MII_ACC—MII Access Register Offset: Default Value: This register is used to control the Management cycles to the PHY. BITS 31-16 Reserved 15-11 PHY Address: For every ...
Page 102
FLOW—Flow Control Register Offset: Default Value: This register controls the generation and reception of the Control (Pause command) frames by the MAC’s flow control block. The control frame fields are selected as specified in the 802.3x Specification and the ...
Page 103
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet 5.4.9 VLAN1—VLAN1 Tag Register Offset: Default Value: This register contains the VLAN tag field to identify VLAN1 frames. For VLAN frames the legal frame length is increased ...
Page 104
WUFF—Wake-up Frame Filter Offset: Default Value: This register is used to configure the wake up frame filter. BITS 31-0 Wake-Up Frame Filter (WFF). Wake-Up Frame Filter (WFF). The Wake-up frame filter is configured through this register using an indexing ...
Page 105
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet 5.5 PHY Registers The PHY registers are not memory mapped. These registers are accessed indirectly through the MAC via the MII_ACC and MII_DATA registers. An index must ...
Page 106
Basic Control Register Index (In Decimal): BITS 15 Reset software reset. Bit is self-clearing. For best results, when setting this bit do not set other bits in this register. 14 Loopback loopback mode ...
Page 107
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet 5.5.2 Basic Status Register Index (In Decimal): BITS 15 100Base-T4 able ability 14 100Base-TX Full Duplex with ...
Page 108
PHY Identifier 2 Index (In Decimal): BITS 15-10 PHY ID Number b. Assigned to the 19th through 24th bits of the OUI Model Number. Six-bit manufacturer’s model number Revision Number. Four-bit manufacturer’s revision ...
Page 109
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet Note 5.2 This default value of this bit is determined by Pin 74 "SPEED_SEL". Please refer to the pin description section for more details. 5.5.6 Auto-negotiation Link ...
Page 110
Auto-negotiation Expansion Index (In Decimal): BITS 15:5 Reserved 4 Parallel Detection Fault fault detected by parallel detection logic fault detected by parallel detection logic 3 Link Partner Next Page Able link partner ...
Page 111
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet 5.5.9 Special Modes Index (In Decimal): ADDRESS 15-8 Reserved 7:5 MODE: PHY Mode of operation. Refer to 4:0 PHYAD: PHY Address: The PHY Address is used for ...
Page 112
Special Control/Status Indications Index (In Decimal): ADDRESS 15 Override AMDIX Strap 0 - AMDIX_EN (pin 73) enables or disables HP Auto MDIX 1 - Override pin 73. PHY Register 27.14 and 27.13 determine MDIX function 14 Auto-MDIX Enable: Only ...
Page 113
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet 5.5.11 Interrupt Source Flag Index (In Decimal): BITS 15-8 Reserved. Ignore on read. 7 INT7. 1= ENERGYON generated, 0= not source of interrupt 6 INT6. 1= Auto-Negotiation ...
Page 114
PHY Special Control/Status Index (In Decimal): BITS Reserved 12 Autodone. Auto-negotiation done indication Auto-negotiation is not done or disabled (or not active Auto-negotiation is done 11-5 Reserved. Write as 0000010b, ignore on ...
Page 115
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet Chapter 6 Timing Diagrams 6.1 Host Interface Timing The LAN9218i supports the following host cycles: Read Cycles: PIO Reads (nCS or nRD controlled) PIO Burst Reads (nCS ...
Page 116
REGISTER NAME ID_REV IRQ_CFG INT_STS INT_EN BYTE_TEST FIFO_INT RX_CFG TX_CFG HW_CFG RX_DP_CTRL RX_FIFO_INF TX_FIFO_INF PMT_CTRL GPIO_CFG GPT_CFG GPT_CNT WORD_SWAP FREE_RUN RX_DROP MAC_CSR_CMD MAC_CSR_DATA AFC_CFG E2P_CMD E2P_DATA Revision 1.8 (06-06-07) High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature ...
Page 117
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet 6.1.2 Special Restrictions on Back-to-Back Read Cycles There are also restrictions on specific back-to-back read operations. These restrictions concern reading specific registers after reading resources that have ...
Page 118
PIO Reads PIO reads can be used to access CSRs or RX Data and RX/TX status FIFOs. In this mode, counters in the CSRs are latched at the beginning of the read cycle. Read data is valid as indicated ...
Page 119
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet 6.3 PIO Burst Reads In this mode, performance is improved by allowing DWORD read cycles WORD read cycles back-to-back. PIO Burst Reads ...
Page 120
RX Data FIFO Direct PIO Reads In this mode the upper address inputs are not decoded, and any read of the LAN9218i will read the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a ...
Page 121
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet 6.5 RX Data FIFO Direct PIO Burst Reads In this mode the upper address inputs are not decoded, and any burst read of the LAN9218i will read ...
Page 122
Note Data FIFO Direct PIO Burst Read cycle begins when both nCS and nRD are asserted. The cycle ends when either or both nCS and nRD are deasserted. They may be asserted and deasserted in any order. 6.6 ...
Page 123
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet 6.7 TX Data FIFO Direct PIO Writes In this mode the upper address inputs are not decoded, and any write to the LAN9218i will write the TX ...
Page 124
Reset Timing nRESET Configuration signals Output drive PARAMETER DESCRIPTION T6.1 Reset Pulse Width T6.2 Configuration input setup to nRESET rising T6.3 Configuration input hold after nRESET rising T6.4 Output Drive after nRESET rising Revision 1.8 (06-06-07) High-Performance Single-Chip 10/100 ...
Page 125
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet 6.9 EEPROM Timing The following specifies the EEPROM timing requirements for the LAN9218i: SYMBOL DESCRIPTION t EECLK Cycle time CKCYC t EECLK High time CKH t EECLK ...
Page 126
Chapter 7 Operational Characteristics 7.1 Absolute Maximum Ratings* Output Voltage (VDD_PLL, VDD_CORE) Supply Voltage (VDD_A, VDD_REF, VREG, VDD_IO) Positive voltage on signal pins, with respect to ground Negative voltage on signal pins, with respect to ground Positive voltage on XTAL1/CLKIN, ...
Page 127
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet 7.3 Power Consumption (Device Only) This section provides typical power consumption values for the LAN9218i in various modes of operation. All of these values are preliminary. These ...
Page 128
Power Consumption (Device and System Components) This section provides typical power consumption values for a complete Ethernet interface based on the LAN9218i, including the power dissipated by the magnetics and other passive components. All of these values are preliminary. ...
Page 129
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet 7.5 DC Electrical Specifications Table 7.3 below lists the worst case current consumption for each of the supplies of the LAN9218i. These figures are provided to assist ...
Page 130
Table 7.4 I/O Buffer Characteristics (continued) PARAMETER SYMBOL IO8 Type Buffer Low Input Level V ILI High Input Level V IHI Low Output Level V OL High Output Level V OH OD8 Type Buffer Low Output Level ...
Page 131
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet Table 7.6 10BASE-T Transceiver Characteristics PARAMETER Transmitter Peak Differential Output Voltage Receiver Differential Squelch Threshold Note 7.11 Measured at the line side of the transformer, line replaced ...
Page 132
Note 7.13 Frequency Deviation Over Time is also referred to as Aging. Note 7.14 The total deviation for the Transmitter Clock Frequency is specified by IEEE 802.3u as +/- 50 PPM. Note 7.15 This number includes the pad, the bond ...
Page 133
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet Chapter 8 Package Outline Figure 8.1 100 Pin TQFP Package Definition Table 8.1 100 Pin TQFP Package Parameters MIN NOMINAL 0. ...