TMC2072_07 SMSC [SMSC Corporation], TMC2072_07 Datasheet - Page 30

• Manufacturer Part Number: TMC2072_07
• Manufacturer: SMSC [SMSC Corporation]

NOTE:
Revision 0.1 (06-07-07)
(2-b) Data bus = 8bits , Word mode=ON
(W16 pin=L, WDMD=1 in MODE REG.)
In word mode = ON, to preserve the upper and lower bytes of word data as in the identical packet, COMR4
must be accessed in order of 08h first and 09h second. This restriction applies to both read and write.
Moreover, it is impossible to independently access CP (address = 02h) in RAM independently To access
the CP, a dummy cycle is necessary. Refer to section 2.5.3 - Packet Data Structure for detail.
COMR2 Register : RDDATA AUTOINC nWRAPAR PAGE[4:0]
COMR3 Register : Address within a page RAMADR[7:0]
COMR4 Register : Packet Data RAMDT[15:0]
A/AD[5:0] = 04h (05h) *
A/AD[5:0] = 06h (07h) *
A/AD[5:0] = 08h (09h) *
A/AD[5:0] = 09h (08h) *
( )*:nSWAP=L
DATASHEET
RD. A.I. nW.A 4
15
7
Page 30
14
6
13
Bit0 is fixed in 0 in the inside.
5
12
4
11
3
3
10
2
2
1
1
9
Peripheral Mode CircLink™ Controller
X
8
0
7
6
5
SMSC TMC2072
4
Datasheet
3
2
1
0