TMC2072_07 SMSC [SMSC Corporation], TMC2072_07 Datasheet - Page 64

• Manufacturer Part Number: TMC2072_07
• Manufacturer: SMSC [SMSC Corporation]

Peripheral Mode CircLink™ Controller
Datasheet
one packet send at remote buffer mode (TXM = 1 and RTO = 1), this bit becomes 1 by the completion of
one packet send or written send-cancellation-command (01h). This bit also becomes 0 after the first send
command and remains 0 until the TX cancel command is issued. Under this condition the node will
continue to send automatically. This bit becomes 1 when the mode exits from the consecutive automatic
send with the writing of send cancellation command (01h) or RTO bit = 1.The TA bit also exists in bit 0 of
the EC interrupt status register and exactly the same signal as it. This bit can also be set by a software
reset.
- When writing: ARCNET mask register (cleared by software reset)
EXCNAK (bit 3)
This bit is set to 1 and the EXCNAK bit in the COMR1 (Diagnostic register) becomes 1 to generate the
interrupt.
(The COM bit in the EC interrupt mask register = 1)
RECON (bit 2)
This bit is set to 1 and the RECON bit in the status register (COMR0) becomes 1 to generate the interrupt.
(The COM bit in the EC interrupt mask register = 1)
NXTIDERR (bit 1)
This bit is set to 1 and the NXTIDERR bit in the diagnostic register (COMR1) becomes 1 to generate the
interrupt.
(The COM bit in the EC interrupt mask register = 1)
TA (bit 0)
This bit is set to 1 and the TA bit in the status register (COMR0) becomes 1 to generate the interrupt.
(The COM bit in the EC interrupt mask register = 1)
Revision 0.1 (06-07-07)
Page 64
SMSC TMC2072
DATASHEET