FDC37C669_07 SMSC [SMSC Corporation], FDC37C669_07 Datasheet - Page 10

• Manufacturer Part Number: FDC37C669_07
• Description: PC 98/99 Compliant Super I/O Floppy Disk Controller with Infrared Support
• Manufacturer: SMSC [SMSC Corporation]

PIN NO.
TQFP
82,92
80,90
85,87
QFP/
nClear to Send
nData Set Ready nDSR1
nData Carrier
Detect
NAME
DESCRIPTION OF PIN FUNCTIONS
nCTS1
nCTS2
nDSR2
nDCD1
nDCD2
SYMBOL
BUFFER
TYPE
I
I
I
10
Active low Clear to Send inputs for the serial
port. Handshake signal which notifies the
UART that the modem is ready to receive
data. The CPU can monitor the status of
nCTS signal by reading bit 4 of Modem
Status Register (MSR). A nCTS signal state
change from low to high after the last MSR
read will set MSR bit 0 to a 1. If bit 3 of
Interrupt Enable Register is set, the interrupt
is generated when nCTS changes state.
The nCTS signal has no effect on the
transmitter.
complement of nCTS.
Active low Data Set Ready inputs for the
serial port. Handshake signal which notifies
the UART that the modem is ready to
establish the communication link. The CPU
can monitor the status of nDSR signal by
reading bit 5 of Modem Status Register
(MSR). A nDSR signal state change from
low to high after the last MSR read will set
MSR bit 1 to a 1. If bit 3 of Interrupt Enable
Register is set, the interrupt is generated
when nDSR changes state. Note: Bit 5 of
MSR is the complement of nDSR.
Active low Data Carrier Detect inputs for the
serial port. Handshake signal which notifies
the UART that carrier signal is detected by
the modem.
status of nDCD signal by reading bit 7 of
Modem Status Register (MSR).
signal state change from low to high after
the last MSR read will set MSR bit 3 to a 1.
If bit 3 of Interrupt Enable Register is set,
the interrupt is generated when nDCD
changes state. Note: Bit 7 of MSR is the
complement of nDCD.
Note:
DESCRIPTION
The CPU can monitor the
Bit 4 of MSR is the
A nDCD