FDC37C669_07 SMSC [SMSC Corporation], FDC37C669_07 Datasheet - Page 93

• Manufacturer Part Number: FDC37C669_07
• Description: PC 98/99 Compliant Super I/O Floppy Disk Controller with Infrared Support
• Manufacturer: SMSC [SMSC Corporation]

8.
9.
EPP 1.9 Read
The timing for a read operation (data) is shown
in timing diagram EPP Read Data cycle.
IOCHRDY is driven active low at the start of
each EPP read and is released when it has been
determined that the read cycle can complete.
The read cycle can complete under the following
circumstances:
1.
2.
Read Sequence of Operation
1.
2.
3.
4.
5.
6.
7.
8.
Peripheral asserts nWAIT, indicating to the
host that any hold time requirements have
been satisfied and acknowledging the
termination of the cycle.
Chip may modify nWRITE and nPDATA in
preparation for the next cycle.
If the EPP bus is not ready (nWAIT
active low) when nDATASTB goes active
then the read can complete when nWAIT
goes inactive high.
If the EPP bus is ready (nWAIT is inactive
high) then the chip must wait for it to go
active low before changing the state of
WRITE or before nDATASTB goes active.
The read can complete once nWAIT
determined inactive.
The host selects an EPP register and drives
nIOR active.
The chip drives IOCHRDY inactive (low).
If WAIT is not asserted, the chip must wait
until WAIT is asserted.
The chip tri-states the PData bus and
deasserts nWRITE.
Chip asserts nDATASTB or nADDRSTRB
indicating that PData bus is tri-stated, PDIR
is set and the nWRITE signal is valid.
Peripheral drives PData bus valid.
Peripheral deasserts nWAIT,
begin the termination phase of the cycle.
a)
that PData is valid and the chip may
The chip latches the data from the
PData
bus
for
the
SData
indicating
bus,
is
is
93
9.
10. Chip may modify nWRITE, PDIR
EPP 1.7 OPERATION
When the EPP 1.7 mode is selected in the
configuration register, the standard and bi-
directional modes are also available. If no EPP
Read, Write or Address cycle is currently
executing, then the PDx bus is in the standard or
bi-directional mode, and all output signals
(STROBE, AUTOFD, INIT) are as set by the
SPP Control Port and direction is controlled by
PCD of the Control port.
In EPP mode, the system timing is closely
coupled to the EPP timing. For this reason, a
watchdog timer is required to prevent system
lockup. The timer indicates if more than 10usec
have elapsed from the start of the EPP cycle
(nIOR or nIOW asserted) to the end of the
cycle nIOR or nIOW deasserted). If a time-out
occurs, the current EPP cycle is aborted and the
time-out condition is indicated in Status bit 0.
Software Constraints
Before an EPP cycle is executed, the software
must ensure that the control register bits D0, D1
and D3 are set to zero. Also, bit D5 (PCD) is a
logic "0" for an EPP write or a logic "1" for and
EPP read.
EPP 1.7 Write
The timing for a write operation (address or
data) is shown in timing diagram EPP 1.7 Write
b)
Peripheral tri-states the PData bus and
asserts nWAIT, indicating to the host that
the PData bus is tri-stated.
nPDATA in preparation for the next cycle.
deasserts nDATASTB or nADDRSTRB,
termination phase.
The chip drives the valid data onto the
SData bus and asserts (releases)
IOCHRDY
complete the read cycle.
this marks the beginning of the
allowing
the
host
and
to