FDC37C669_07 SMSC [SMSC Corporation], FDC37C669_07 Datasheet - Page 131

• Manufacturer Part Number: FDC37C669_07
• Description: PC 98/99 Compliant Super I/O Floppy Disk Controller with Infrared Support
• Manufacturer: SMSC [SMSC Corporation]

CR12-CR1D
These registers are reserved. The default value
of these registers after power up is 00H.
CR1E
This register can only be accessed in the
Configuration Mode and after the CSR has been
Upper Address Decode requirements: nCS='0' and A10='0' are required to qualify the GAMECS
output.
CR03, bit DB0 is the PWRGD/GAMECS control bit and overrides the selection made by the above
configuration.
ADR9
DB7
ADR8
DB6
ADR7
DB5
DB1
0
0
1
1
DB0
0
1
0
1
ADR6
DB4
16 byte block decode,
131
8 Byte block decode,
ADR[3:0] = XXXXb
GAMECS disabled
ADR[3:0] = 0XXXb
ADR[3:0] = 0001b
Configuration
1 Byte decode,
initialized to 1EH.
register after power up is 80H. This register is
used to select the base address of the Game
Chip Select decoder (GAMECS). The GAMECS
can be set to 48 locations, on 16 byte
boundaries from 100H-3F0H.
GAMECS, set DB1 and DB0 to zero.
ADR5
GAMECS
DB3
ADR4
DB2
The default value of this
DB1
GAMECS Config
To disable the
DB0