LPC47M182-NR SMSC [SMSC Corporation], LPC47M182-NR Datasheet
LPC47M182-NR
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LPC47M182-NR Summary of contents
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... Reduced Power Consumption − DMA Enable Logic − Data Rate and Drive Control Registers 480 Address Eight IRQ and Three DMA Options SMSC LPC47M182 LPC47M182 Advanced I/O Controller with Motherboard GLUE Logic Enhanced Digital Data Separator − 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data Rates − ...
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... LPC47M182-NR for 128 pin QFP package LPC47M182-NW for 128 pin QFP package (green, lead-free) 80 Arkay Drive Hauppauge, NY 11788 (631) 435-6000 FAX (631) 273-3123 Copyright © SMSC 2005. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given ...
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... STATUS REGISTER A (SRA) ................................................................................................................39 6.4.4 STATUS REGISTER B (SRB) ................................................................................................................40 6.4.5 DIGITAL OUTPUT REGISTER (DOR) ...................................................................................................42 6.4.6 TAPE DRIVE REGISTER (TDR) ............................................................................................................44 6.4.7 DATA RATE SELECT REGISTER (DSR) ..............................................................................................45 6.4.8 MAIN STATUS REGISTER ....................................................................................................................47 6.4.9 DATA REGISTER (FIFO) .......................................................................................................................48 6.4.10 DIGITAL INPUT REGISTER (DIR)......................................................................................................49 6.4.11 CONFIGURATION CONTROL REGISTER (CCR) .............................................................................50 6.4.12 STATUS REGISTER ENCODING ......................................................................................................51 SMSC LPC47M182 3 Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) DATASHEET ...
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... Effect Of The Reset on Register File...................................................................................................87 6.29.2 FIFO INTERRUPT MODE OPERATION.............................................................................................88 6.29.3 FIFO POLLED MODE OPERATION ...................................................................................................88 Chapter 7 Notes On Serial Port Operation........................................................................................ 93 7.1 FIFO Mode Operation: ...................................................................................................................... 93 7.1.1 GENERAL ..............................................................................................................................................93 7.1.2 TX AND RX FIFO OPERATION .............................................................................................................93 7.2 Infrared Interface ............................................................................................................................... 94 Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) Advanced I/O Controller with Motherboard GLUE Logic 4 DATASHEET Datasheet SMSC LPC47M182 ...
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... Timing Diagrams For SER_IRQ Cycle ..............................................................................................115 7.23.2 SER_IRQ Cycle Control....................................................................................................................115 7.23.3 SER_IRQ Data Frame ......................................................................................................................116 7.23.4 Stop Cycle Control ............................................................................................................................117 7.23.5 Latency .............................................................................................................................................117 7.23.6 EOI/ISR Read Latency......................................................................................................................117 7.23.7 AC/DC Specification Issue ................................................................................................................117 7.23.8 Reset and Initialization ......................................................................................................................117 7.24 Interrupt Generating Registers..................................................................................................... 117 SMSC LPC47M182 5 Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) DATASHEET ...
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... SCK_BJT_GATE Output.............................................................................................................. 146 7.39 Backfeed Cut and Latched Backfeed Cut Circuitry...................................................................... 147 7.40 Resume Reset Logic.................................................................................................................... 152 7.41 CNR Logic.................................................................................................................................... 152 Chapter 8 Power Control Runtime Registers .................................................................................. 154 Chapter 9 GPIO Runtime Registers................................................................................................. 161 Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) Advanced I/O Controller with Motherboard GLUE Logic 6 DATASHEET Datasheet SMSC LPC47M182 ...
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... Chapter 15 Board Test Mode........................................................................................................... 221 Chapter 16 Reference Documents ................................................................................................... 223 List of Figures Figure 2.1 - LPC47M182 Pin Layout ............................................................................................................................12 Figure 4.1 – LPC47M182 Block Diagram.....................................................................................................................29 Figure 7.1 – NKBDRST Circuit...................................................................................................................................124 Figure 7.2 – Keyboard Latch ......................................................................................................................................125 Figure 7.3 – Mouse Latch ..........................................................................................................................................125 Figure 7.4 – GPIO Function Illustration ......................................................................................................................130 Figure 7.5 – ...
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... Figure 14.1 - 128 Pin QFP Package Outline, 14x20x2.7 Body, 3.2MM Footprint ......................................................220 Figure 15.1 – Example XOR Chain Circuitry..............................................................................................................221 List of Tables Table 3.1 - LPC47M182 Pin Description ......................................................................................................................14 Table 3.2 – Pins with Internal Resistors .......................................................................................................................23 Table 3.3 – Pins that Require External Resistors.........................................................................................................24 Table 3.4 – Default State of Pins..................................................................................................................................25 Table 6.1 – ...
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... Table 7.42 – SCK_BJT_GATE Truth Table ...............................................................................................................146 Table 7.43 – nBACKFEED_CUT and LATCHED_BF_CUT Pins ...............................................................................147 Table 7.44 – nBACKFEED_CUT Truth Table ............................................................................................................147 Table 7.45 – LATCHED_BF_CUT Truth Table ..........................................................................................................148 Table 7.46 – Latched Backfeed Cut Power Up Sequence Timing .............................................................................149 SMSC LPC47M182 9 Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) DATASHEET ...
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... Table 9.2 – GPIO Runtime Registers Description, LD_NUM = 0 ...............................................................................162 Table 10.1 – Runtime Register Block Runtime Registers Summary ..........................................................................165 Table 11.1– LPC47M182 Configuration Registers Summary, LD_NUM bit = 0 .........................................................170 Table 11.2 – LPC47M182 Configuration Register Summary, LD_NUM bit = 1 .........................................................172 Table 11.3 – Chip Level Registers .............................................................................................................................174 Table 11.4 – Logical Device Registers.......................................................................................................................177 Table 11.5 – ...
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... IRQ1 through IRQ15 on the Serial IRQ Interface. The LPC47M182’s Enhanced Digital Data Separator does not require any external filter components and is therefore easy to use and offers lower system costs and reduced board area. The LPC47M182 is register compatible with SMSC’s proprietary 82077AA core. ...
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... Pin 117 is used to select the mode of the logical device numbering. This pin affects the LD_NUM bit in the TEST 7 register (configuration register 0x29), which is used to select logical device numbering in the LPC47M182. The pin functions as follows: Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) Advanced I/O Controller with Motherboard GLUE Logic LPC47M182 128 PIN QFP Figure 2.1 - LPC47M182 Pin Layout 12 DATASHEET Datasheet 102 nCDC_DWN_RST 101 ...
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... Connecting this pin to VTR will select the SMSC mode of the logical device numbering. This configuration sets the LD_NUM bit to ‘1’ and the associated functionality corresponds to the existing functionality in the part when the LD_NUM bit=1. SMSC LPC47M182 13 Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) ...
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... Active low input used as LPC Interface Reset. 3.3V and 5V buffered copy of PCI Reset signal is available on nPCIRST_OUT and nIDE_RSTDRV. These pins are listed under GLUE PINS. Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) Table 3.1 - LPC47M182 Pin Description DESCRIPTION POWER AND GROUND PINS (20) CLOCKS (2) PROCESSOR/HOST LPC INTERFACE (11) 14 ...
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... Can be configured as an Open-Drain Output. 16 nSTEP Step Pulse Output. This active low high current driver issues a low pulse for each track-to-track movement of the head. Can be configured as an Open-Drain Output. SMSC LPC47M182 BUFFER DESCRIPTION NAME (NOTE 2) OD8 FDD INTERFACE (14) IS O12 ...
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... Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) Advanced I/O Controller with Motherboard GLUE Logic DESCRIPTION O12 O12 O12 IS O12 O12 SERIAL PORT 1 INTERFACE ( DATASHEET Datasheet BUFFER PWR NAME WELL NOTES (NOTE 2) (NOTE 3) VCC VCC VCC VCC VCC VCC VCC VCC VCC SMSC LPC47M182 ...
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... Note: Bit 6 of MSR is the complement of nRI. 118 nRI2 Active low Ring Indicator input for serial port 2. See description for nRI1. 119 RXD2 Receiver serial data input. 120 TXD2 Transmit serial data output. SMSC LPC47M182 DESCRIPTION O8 O12 SERIAL PORT 2 INTERFACE (8) IPD ISPD_400 O12 17 Revision 1 ...
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... PARALLEL PORT INTERFACE (17 IOP14 IOP14 IOP14 IOP14 IOP14 IOP14 IOP14 IOP14 18 DATASHEET Datasheet BUFFER PWR NAME WELL NOTES (NOTE 2) (NOTE 3) VCC 10 VCC VCC 10 VCC VCC 10 VCC 10 VCC 9 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC SMSC LPC47M182 ...
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... Hard Drive Front Panel LED Open-Drain Output 67 nPRIMARY_ IDE Primary Drive Active Input HD 68 nSECONDARY IDE Secondary Drive Active Input _HD 69 nSCSI SCSI Drive Active Input SMSC LPC47M182 DESCRIPTION I OP14 OP14 OP14 OP14 KEYBOARD/MOUSE INTERFACE (6) IOD24 IOD24 IOD24 IOD24 OD8 OD8 ...
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... GENERAL PURPOSE I/O (8) ISO8 20 DATASHEET Datasheet PWR WELL NOTES (NOTE 3) VTR VTR VTR VTR 3 VTR VTR 3 VTR 3 VTR VTR VTR VTR VTR VTR VTR VTR VTR VTR VTR VTR 6 VTR VTR VTR VTR VTR VTR VTR VTR 6 SMSC LPC47M182 ...
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... IS0D8. Note 9: The IRTX2 pin is driven low upon power-up of VCC. This pin will remain low following a power-up (VCC POR) until it is selected via the IR MUX bits and serial port 2 is enabled by setting the activate bit, at which SMSC LPC47M182 DESCRIPTION (NOTE 2) IO8 ...
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... TEST 7 register (configuration register 0x29), which is used to select logical device numbering in the LPC47M182. The pin has an internal pull-down resistor that selects the non-SMSC mode. To select this mode, the pin should be left unconnected. Connecting this pin to VTR will select the SMSC mode of the logical device numbering ...
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... Pins With Internal Resistors The following pins have internal resistors: SIGNAL NAME nCPU_PRESENT nFPRST nPRIMARY_HD PWRGD_PS nSCSI nSECONDARY_HD TEST_EN SMSC LPC47M182 Table 3.2 – Pins with Internal Resistors RESISTOR VALUE 30uA Pull-up to VTR 30uA Pull-up to VTR 30uA Pull-up to VCC 30uA Pull-up to VTR ...
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... Pull-up to V_5P0_STBY 1 kohm Pull-up to V_5P0_STBY 1 kohm Pull-up to V_5P0_STBY 10 kohm Pull-down to VSS 220 ohm Pull-up to VTR 330 ohm Pull-up to VCC 4.7 kohm Pull-up to VCC 4.7 kohm Pull-up to VCC 2.2 kohm Pull-up to VCC5V 2.2 kohm Pull-up to VCC5V 2.7 kohm Pull-up to VCC 2.7 kohm Pull-up to VTR 24 DATASHEET Datasheet NOTES SMSC LPC47M182 ...
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... VCC SER_IRQ VCC nLDRQ VCC nLFRAME VCC LAD[0:3] VCC nDSKCHG VCC nHDSEL VCC SMSC LPC47M182 RESISTOR VALUE 2.7 kohm Pull-up to VCC 2.7 kohm Pull-up to VTR 220 ohm Pull-up to VTR design-dependant Pull-up to appropriate voltage (not to exceed 5V) Table 3.4 – Default State of Pins PCI RESET VCC POR ...
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... VSS until Serial Port 2 is enabled. This pin is internally pulled down to VSS until Serial Port 2 is enabled. This pin is internally pulled down to VSS until Serial Port 2 is enabled. This pin is internally pulled down to VSS until Serial Port 2 is enabled. SMSC LPC47M182 ...
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... VTR FAN_TACH2 SMB_CLK_M VTR SMB_CLK_R VTR SMB_DAT_M VTR SMB_DAT_R VTR VTR DDCSDA_5V SMSC LPC47M182 PCI RESET VCC POR VTR POR Out – High Out – High Off Out – High Out – High Off Out – High Out – High Off ...
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... VCC5V. The DDC and GPIO functions are multiplexed on the same pin with DDC as the default function. DDC function requires external pull-up to VCC. Test Mode pin. This pin has internally pull-down to VSS. External pull-up required to enable the test mode. SMSC LPC47M182 ...
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... V_5P0_STBY Configuration Registers nPCI_RESET SMSC PROPRIETARY 82077 COMPATIBLE VGA VERTICAL FLOPPYDISK SMBus CONTROLLER CORE Voltage Isolation Translation Figure 4.1 – LPC47M182 Block Diagram 29 Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) DATASHEET XOR-Chain PD[7:0] BUSY, SLCT, PE, Multi-Mode nERROR, nACK Parallel Port with ChiProtect TM nSTROBE, nINITP, nSLCTIN, nALF ...
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... Volt Operation / 5 Volt Tolerance The LPC47M182 is a 3.3 Volt part intended solely for 3.3V applications. Non-LPC bus pins are 5V tolerant; that is, the operating input voltage is 5.5V max, and the I/O buffer output pads are backdrive protected (they do not impose a load on any external VCC powered circuitry). ...
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... Indication of 32KHZ Clock There is a bit to indicate whether or not the 32kHz clock input is connected to the LPC47M182. This bit is located at bit 0 of the CLOCKI32 configuration register at 0xF0 in the Power Control Logical Device (when LD_NUM=0) or Runtime Register Block Logical Device (when LD_NUM=1). This register is powered by VTR and reset on a VTR POR ...
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... VCC cycles on and off. When the internal PWRGOOD signal is “1” (active), VCC > 2.3V (nominal), and the LPC47M182 host interface is active. When the internal PWRGOOD signal is “0” (inactive), VCC <= 2.3V (nominal), and the LPC47M182 host interface is inactive; that is, LPC bus reads and writes will not be decoded. ...
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... Advanced I/O Controller with Motherboard GLUE Logic Datasheet Chapter 6 Functional Description The following sections describe the functional blocks located in the LPC47M182 (see Figure 4.1). The various Super I/O components are described in the following sections and their registers are implemented as typical Plug-and-Play components (see section Chapter 11 − Configuration on page 167). 6.1 Super I/O Registers Table 6 ...
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... Host Processor Interface (LPC) The host processor communicates with the LPC47M182 through a series of read/write registers via the LPC interface. The port addresses for these registers are shown in Table 6.1. Register access is accomplished through I/O cycles or DMA transfers. All registers are 8 bits wide. 6.3 LPC Interface The following sub-sections specify the implementation of the LPC bus ...
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... NLFRAME Usage nLFRAME is used by the host to indicate the start of cycles and the termination of cycles due to an abort or time-out condition. This signal used by the LPC47M182 to know when to monitor the bus for a cycle. This signal is used as a general notification that the LAD[3:0] lines contain information relative to the start or stop of a cycle, and that the LPC47M182 monitors the bus to determine whether the cycle is intended for it ...
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... SYNC pattern upon recognizing the cycle. The host immediately drives the sync pattern for write cycles. If the LPC47M182 needs to assert wait states, it does so by driving 0101 or 0110 on LAD[3:0] until it is ready, at which point it will drive 0000 or 1001. The LPC47M182 will choose to assert 0101 or 0110, but not switch between the two patterns. ...
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... The LPC47M182 reports errors via the LAD[3:0] = 1010 SYNC encoding. If the host was reading data from the LPC47M182, data will still be transferred in the next two nibbles. This data may be invalid, but it will be transferred by the LPC47M182. If the host was writing data to the LPC47M182, the data had already been transferred. ...
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... R/W Digital Output Register (DOR) 373 R/W Tape Drive Register (TDR) 374 R Main Status Register (MSR) 374 W Data Rate Select Register (DSR) 375 R/W Data (FIFO) 376 Reserved 377 R Digital Input Register (DIR) 377 W Configuration Control Register (CCR) 38 DATASHEET Datasheet REGISTER SMSC LPC47M182 ...
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... Active high status of the STEP output disk interface output pin. BIT 6 nDRV2 This function is not supported. This bit is always read as “1”. BIT 7 INTERRUPT PENDING Active high bit indicating the state of the Floppy Disk Interrupt output. PS/2 Model 30 Mode SMSC LPC47M182 STEP nTRK0 ...
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... The SRB can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 – D7 are held in a high impedance state for a read of address 3F1. PS/2 Mode Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) Advanced I/O Controller with Motherboard GLUE Logic DRQ STEP TRK0 nHDSEL INDEX F N DATASHEET Datasheet nDIR N/A N/A 1 SMSC LPC47M182 ...
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... BIT 6 RESERVED Always read as a logic “1”. BIT 7 RESERVED Always read as a logic “1” PS/2 Model 30 Mode 7 nDRV2 RESET N/A COND. BIT 0 nDRIVE SELECT 2 The DS2 disk interface is not supported. SMSC LPC47M182 DRIVE WDATA RDATA SEL0 TOGGLE TOGGLE 1 ...
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... These two bits are binary encoded for the drive selects, thereby allowing only one drive to be selected at one time. BIT 2 nRESET Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) Advanced I/O Controller with Motherboard GLUE Logic MOT MOT DMAEN nRESET EN1 EN0 DATASHEET Datasheet DRIVE DRIVE SEL1 SEL0 SMSC LPC47M182 ...
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... Bit1 BIT 6 MOTOR ENABLE 2 The MTR2 disk interface output is not supported in the LPC47M182. BIT 7 MOTOR ENABLE 3 The MTR3 disk interface output is not supported in the LPC47M182. SMSC LPC47M182 DRIVE DOR VALUE 0 1CH 1 2DH DRIVE SELECT OUTPUTS (ACTIVE LOW) ...
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... L0-CRF2 – L0-CRF2 – DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet The TDR DB2 DB1 DB0 0 tape sel1 tape sel0 DB2 DB1 DB0 tape sel1 tape sel0 Bit 4 L0-CRF2 – B0 L0-CRF2 – B2 L0-CRF2 – B4 L0-CRF2 – B6 SMSC LPC47M182 ...
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... Table 6.7 shows the precompensation values for the combination of these bits settings. Track 0 is the default starting track number to start precompensation. This starting track number can be changed by the configure command. BIT 5 UNDEFINED Should be written as a logic “0”. SMSC LPC47M182 ...
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... DRATE1 DRATE0 46 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet DRATE(1) DENSEL DRIVE TYPE 4/2/1 MB 3.5” 2/1 MB 5.25” FDDS 2/1.6/1 MB 3.5” (3-MODE) PS/2 SMSC LPC47M182 ...
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... BIT 6 DIO Indicates the direction of a data transfer once a RQM is set indicates a read and a 0 indicates a write is required. BIT 7 RQM Indicates that the host can transfer data if set access is permitted if set SMSC LPC47M182 PRECOMPENSATION DATA RATE DELAYS 2 Mbps 20 ...
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... Mbps DATA RATE 118.5 us MAXIMUM DELAY TO SERVICING AT 500 Kbps DATA RATE 126 1 238 DATASHEET Datasheet This maintains PC/AT SMSC LPC47M182 ...
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... This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value programmed in the Force Disk Change Register. This register is located in the Power Control Logical Device (when LD_NUM=0) or Runtime Register Block Logical Device (when LD_NUM=1)at offset 0x18. SMSC LPC47M182 ...
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... Should be set to a logical “0” Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05 DMAEN NOPREC DRATE N/A N/A N/A N/A 50 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet DRATE SEL1 SEL0 DRATE DRATE SEL1 SEL0 N SMSC LPC47M182 ...
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... During the Result Phase of certain commands, the Data Register contains data bytes that give the status of the command just executed. BIT NO. SYMBOL 7 1,0 DS1,0 SMSC LPC47M182 N/A N/A N/A N/A Table 6.12 - Status Register 0 NAME Interrupt Code 00 - Normal termination of command. The specified command was properly executed and completed without error ...
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... FF hex, which indicates a bad track with a hard error according to the IBM soft-sectored format. Missing Data The FDC cannot detect a data address mark or a Address Mark deleted data address mark. 52 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet SMSC LPC47M182 ...
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... Interface Mode bits in FDC logical device -CRF0[3,2]. 6.5.1 PC/AT mode The PC/AT register set is enabled, the DMA enable bit of the DOR becomes valid (controls the interrupt and DMA functions), and DENSEL is an active high signal. SMSC LPC47M182 Table 6.15 - Status Register 3 NAME DESCRIPTION Unused. This bit is always "0". ...
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... FDC when service is requested from the host and ranges from 1 to 16. The parameter FIFOTHR, which the user programs, is one less and ranges from 0 to 15. Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) Advanced I/O Controller with Motherboard GLUE Logic 54 DATASHEET Datasheet SMSC LPC47M182 ...
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... The generation of the interrupt determines the beginning of the result phase. For each of the commands, a defined set of result bytes has to be read from the FDC before the result phase is complete. These bytes of data must be read out for another command to start. SMSC LPC47M182 55 Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) ...
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... The time interval that FDC waits after loading the head and before initializing a read or write operation. Refer to the Specify command for actual delays. The time interval from the end of the execution phase (of a read or write command) until the head is unloaded. Refer to the Specify command for actual delays. 56 DATASHEET Datasheet SMSC LPC47M182 ...
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... Number SC Number of Sectors Per Track SK Skip Flag SMSC LPC47M182 DESCRIPTION Lock defines whether EFIFO, FIFOTHR, and PRETRK parameters of the CONFIGURE COMMAND can be reset to their default values by a “software Reset”. (A reset caused by writing to the appropriate bits of either the DSR or DOR) A one selects the double density (MFM) mode. A zero selects single density (FM) mode ...
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... Mbit data rate. Refer to the SPECIFY command for actual delays. Registers within the FDC which store status information after a command has been executed. This status information is available to the host during the result phase after command execution. Alters timing allow for pre-erase loads in perpendicular drives. 58 DATASHEET Datasheet SMSC LPC47M182 ...
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... PHASE R/W D7 Command W MT MFM Execution Result SMSC LPC47M182 Table 6.17 - Instruction Set READ DATA DATA BUS HDS DS1 DS0 EOT GPL DTL ST0 ...
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... FDD and system. Status information after Com- mand execution. Sector ID information after Command execution. D0 REMARKS 1 Command Codes DS0 Sector ID information prior to Command execution. Data transfer between the FDD and system. Status information after Command execution. Sector ID information after Command execution. SMSC LPC47M182 ...
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... Result PHASE R/W D7 Command W MT MFM Execution Result SMSC LPC47M182 READ A TRACK DATA BUS MFM HDS DS1 EOT GPL DTL ST0 ST1 ST2 C ...
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... DS0 Bytes/Sector Sectors/Cylinder Gap 3 Filler Byte Input Sector Parameters FDC formats an entire cylinder Status information after Command execution D0 REMARKS 1 Command Codes DS0 Head retracted to Track 0 Interrupt. REMARKS Command Codes Status information at the end of each seek operation. REMARKS 1 Command Codes SMSC LPC47M182 ...
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... Execution W PHASE R/W D7 Command PHASE R/W D7 Command W 0 Execution Result LOCK SMSC LPC47M182 SENSE DRIVE STATUS DATA BUS HDS DS1 ST3 SEEK DATA BUS ...
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... Cylinder is stored in Data Register Status information after Command execution. Disk status after the Command has completed D0 REMARKS 0 Command Codes WGATE D0 REMARKS Invalid Command Codes (NoOp – FDC goes into Standby State) ST0 = 80H D1 D0 REMARKS Command Codes SMSC LPC47M182 ...
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... Sector 1, Side 0 and completing the last sector of the same track at Side 1. If the host terminates a read or write operation in the FDC, the ID information in the result phase is dependent upon the state of the MT bit and EOT byte. Refer to Table 6.19. SMSC LPC47M182 Upon receipt of the TC cycle implied TC (FIFO Table 6.18 - Sector Sizes N ...
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... CM BIT OF READ? ST2 SET? Yes No Yes Yes Yes No No Yes 66 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet DESCRIPTION OF RESULTS Normal termination. Address not incremented. Next sector not searched for. Normal termination. Normal termination. Sector not read (“skipped”). SMSC LPC47M182 ...
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... Less than EOT Equal to EOT 1 Less than EOT Equal to EOT NC: No Change, the same value as the one at the beginning of command execution. LSB: Least Significant Bit, the LSB complemented. SMSC LPC47M182 RESULTS SECTOR CM BIT OF READ? ST2 SET? Yes Yes Yes ...
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... Sectors Per Side = Number of formatted sectors per each side of the disk. # Sectors Remaining = Number of formatted sectors left which can be read, including side 1 of the disk set to “1”. Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) Advanced I/O Controller with Motherboard GLUE Logic 68 DATASHEET Datasheet SMSC LPC47M182 ...
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... Table 6.24 contains typical values for gap fields that are dependent upon the size of the sector and the number of sectors on each track. Actual values can vary due to drive electronics. SMSC LPC47M182 SC/EOT VALUE TERMINATION RESULT ...
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... ... ... 256 256 512 ... ... 128 256 512 256 SMSC LPC47M182 Datasheet ...
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... After each step pulse is issued, NCN is compared against PCN, and when NCN = PCN the SE bit in Status Register 0 is set to “1” and the command is terminated. During the command phase of the seek or recalibrate operation, the FDC is in the BUSY state, but during the execution phase the SMSC LPC47M182 71 Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) ...
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... Status is not issued, the drive will continue to be BUSY and may affect the operation of the next command. Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05 INTERRUPT DUE Polling 1 00 Normal termination of Seek or Recalibrate command Abnormal termination of Seek or Recalibrate 1 01 command 72 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet SMSC LPC47M182 ...
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... POLL - Polling Enabled FIFOTHR - FIFO Threshold Set to 1 Byte PRETRK - Pre-Compensation Set to Track 0 EIS - Enable Implied Seek. When set to "1", the FDC will perform a Seek operation before executing a read or write command. Defaults to no implied seek. SMSC LPC47M182 HUT 500K 300K 250K ...
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... The user simply needs to issue a second Recalibrate command. The Seek command and implied seeks will function correctly within the 44 (D) track (299-255) area of the “extended track area” the user’s Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) Advanced I/O Controller with Motherboard GLUE Logic DIR ACTION 0 Step Head Out 1 Step Head In 74 DATASHEET Datasheet SMSC LPC47M182 ...
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... The perpendicular mode command is enhanced to allow specific drives to be designated Perpendicular recording drives. This enhancement allows data transfers between Conventional and Perpendicular drives without having to issue Perpendicular mode commands between the accesses of the different drive types, nor having to change write pre-compensation values. SMSC LPC47M182 75 Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) DATASHEET ...
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... DOR or DSR registers) will only clear GAP and WGATE bits to “0”. D0-D3 are unaffected and retain their previous value. “Hardware” resets will clear all bits (GAP, WGATE and D0-D3) to “0”, i.e all conventional mode. Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) Advanced I/O Controller with Motherboard GLUE Logic 76 DATASHEET Datasheet SMSC LPC47M182 ...
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... COMPATIBILITY The LPC47M182 was designed with software compatibility in mind fully backwards- compatible solution with the older generation 765A/B disk controllers. The FDC also implements on-board registers for compatibility with the PS/2, as well as PC/AT and PC/XT, floppy disk controller subsystems. After a ...
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... Interrupt Enable (read/write Interrupt Identification (read FIFO Control (write Line Control (read/write Modem Control (read/write Line Status (read/write Modem Status (read/write Scratchpad (read/write Divisor LSB (read/write Divisor MSB (read/write 78 DATASHEET Datasheet SMSC LPC47M182 ...
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... Disabling the interrupt system inhibits the Interrupt Identification Register and disables any Serial Port interrupt out of the LPC47M182. All other system functions operate in their normal manner, including the Line Status and MODEM Status Registers. The contents of the Interrupt Enable Register are described below ...
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... They are in descending order of priority: Receiver Line Status (highest priority) Received Data Ready Transmitter Holding Register Empty Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) Advanced I/O Controller with Motherboard GLUE Logic 80 DATASHEET Datasheet Clearing this bit to a logic “0” SMSC LPC47M182 ...
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... In non-FIFO mode, this bit is a logic “0”. In FIFO mode this bit is set along with bit 2 when a timeout interrupt is pending. Bits 4 and 5 These bits of the IIR are always logic “0”. Bits 6 and 7 These two bits are set when the FIFO CONTROL Register bit 0 equals 1. SMSC LPC47M182 RCVR FIFO Bit 7 Bit 6 Trigger Level (BYTES) 0 ...
Page 82
... INTERRUPT RESET CONTROL - Reading the Line Status Register Read Receiver Buffer or the FIFO drops below the trigger level. Reading the Receiver Buffer Register Reading the IIR Register (if Source of Interrupt) or Writing the Transmitter Holding Register Reading the MODEM Status Register SMSC LPC47M182 ...
Page 83
... Set Break Control bit. When bit logic “1”, the transmit data output (TXD) is forced to the Spacing or logic “0” state and remains there (until reset by a low level bit 6) regardless of other transmitter activity. This feature enables the Serial Port to alert a terminal in a communications system. SMSC LPC47M182 BIT 1 BIT 0 ...
Page 84
... Interrupts are also operational but the interrupts’ sources are now the lower four bits of the MODEM Control Register instead of the MODEM Control inputs. The interrupts are still controlled by the Interrupt Enable Register. Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) Advanced I/O Controller with Motherboard GLUE Logic 84 DATASHEET Datasheet SMSC LPC47M182 ...
Page 85
... FIFO. Restarting after a break is received, requires the serial data (RXD logic “1” for at least ½ bit time. Note: Bits 1 through 4 are the error conditions that produce a Receiver Line Status Interrupt whenever any of the corresponding conditions are detected and the interrupt is enabled. SMSC LPC47M182 85 Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) DATASHEET ...
Page 86
... Delta Data Carrier Detect (DDCD). Bit 3 indicates that the nDCD input to the chip has changed state. Note: Whenever bit set to a logic “1”, a MODEM Status Interrupt is generated. Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) Advanced I/O Controller with Motherboard GLUE Logic In the FIFO mode this bit is set whenever the 86 DATASHEET Datasheet SMSC LPC47M182 ...
Page 87
... The input clock to the BRG is a 1.8462 MHz clock. Table 6.30 shows the baud rates possible. 6.29.1 Effect Of The Reset on Register File The Reset Function (details the effect of the Reset input on each of the registers of the Serial Port. SMSC LPC47M182 87 Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) ...
Page 88
... In this mode, the user’s program will check RCVR and XMITTER status via the LSR. LSR definitions for the FIFO Polled Mode are as follows: Bit 0=1 as long as there is one byte in the RCVR FIFO. Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) Advanced I/O Controller with Motherboard GLUE Logic 88 DATASHEET Datasheet SMSC LPC47M182 ...
Page 89
... Note : The percentage error for all baud rates, except where indicated otherwise, is 0.2%. 2 Note : The High Speed bit is located in the Device Configuration Space. SMSC LPC47M182 Table 6.30 - Baud Rates PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL 2304 0.001 1536 1047 857 0 ...
Page 90
... Bit 0 is high; Bits low All bits low All bits low All bits low All bits low except 5, 6 high Bits low; Bits input High Low Low Low High High High High All Bits Low All Bits Low SMSC LPC47M182 ...
Page 91
... Bit 7 of the Line Control Register (ADDR = 3). Note 1: Bit 0 is the least significant bit the first bit serially transmitted or received. Note 2: When operating in the XT mode, this bit will be set any time that the transmitter shift register is empty. SMSC LPC47M182 REGISTER SYMBOL ...
Page 92
... Bit 6 Bit 4 Bit 5 Bit 6 Bit 12 Bit 13 Bit 14 92 DATASHEET Datasheet BIT 6 BIT 7 Data Bit 7 Data Bit 7 0 FIFOs Enabled (Note 5) RCVR Trigger MSB Divisor Latch Access Bit (DLAB) 0 Error in RCVR FIFO (Note 5) Data Carrier Detect (DCD) Bit 7 Bit 7 Bit 15 SMSC LPC47M182 ...
Page 93
... Rx shift register has accessed the Rx FIFO within 4 character times of the last byte. The timeout interrupt is cleared or reset when the CPU reads the Rx FIFO or another character enters it. These FIFO related features allow optimization of CPU/UART transactions and are especially useful given the higher baud rate capability (256 kbaud). SMSC LPC47M182 93 Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) DATASHEET ...
Page 94
... IR Transmit Pins The following description pertains to the TXD2 and IRTX2 pins of the LPC47M182. Following a VCC POR, the TXD2 and IRTX2 pins will be output and low. They will remain low until one of the following conditions are met: ...
Page 95
... Datasheet 7.3 Parallel Port The LPC47M182 incorporates an IBM XT/AT compatible parallel port. This supports the optional PS/2 type bi-directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel port modes. Refer to the Configuration Registers for information on disabling, power down, changing the base address of the parallel port, and selecting the mode of operation ...
Page 96
... PD<0:7> PData<0:7> nACK Intr BUSY nWait PE (User Defined) SLCT (User Defined) nALF nDatastb nERROR (User Defined) nINITP nRESET nSLCTIN nAddrstrb 96 DATASHEET Datasheet ECP nStrobe PData<0:7> nAck Busy, PeriphAck(3) PError, nAckReverse (3) Select nAutoFd, HostAck(3) nFault (1) nPeriphRequest (3) nInit(1) nReverseRqst(3) nSelectIn(1,3) This SMSC LPC47M182 ...
Page 97
... CONTROL PORT ADDRESS OFFSET = 02H The Control Port is located at an offset of ‘02H’ from the base address. The Control Register is initialized by the RESET input, bits only being affected; bits 6 and 7 are hard wired low. SMSC LPC47M182 97 Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) DATASHEET ...
Page 98
... DATA WRITE cycle to be performed, during which the data is latched for the duration of the EPP write cycle. During a READ operation, PD0 - PD7 ports are read. An LPC I/O read cycle causes an EPP READ Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) Advanced I/O Controller with Motherboard GLUE Logic In printer mode, the direction is always out 98 DATASHEET Datasheet SMSC LPC47M182 ...
Page 99
... Control port). If the user leaves PCD as a logic “1”, and attempts to perform an EPP write, the chip is unable to perform the write (because PCD is a logic “1”) and will appear to perform an EPP read on the parallel bus, no error is indicated. SMSC LPC47M182 99 Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) ...
Page 100
... Peripheral tri-states the PData bus and asserts nWAIT, indicating to the host that the PData bus is tri- stated. 9. Chip may modify nWRITE, PDIR and nPDATA in preparation for the next cycle. Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) Advanced I/O Controller with Motherboard GLUE Logic 100 DATASHEET Datasheet SMSC LPC47M182 ...
Page 101
... The Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination phase of the cycle. 7. The chip drives the final sync and deasserts nDATASTB or nADDRSTRB. 8. Peripheral tri-states the PData bus. SMSC LPC47M182 101 Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) DATASHEET ...
Page 102
... This signal is active low. When driven active, the EPP device is reset to its initial operational mode. O This signal is active low used to denote address read or write operation. I Same as SPP mode. I Same as SPP mode. I Same as SPP mode. 102 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet SMSC LPC47M182 ...
Page 103
... Small FIFOs are employed in both forward and reverse directions to smooth data flow and improve the maximum bandwidth requirement. The size of the FIFO is 16 bytes deep. The port supports an automatic handshake for the standard parallel port to improve compatibility mode transfer speed. SMSC LPC47M182 D5 D4 ...
Page 104
... This pin is driven low to place the channel in the reverse direction. The peripheral is only allowed to drive the bi-directional data bus while in ECP Mode and HostAck is low and nSelectIn is high. Always deasserted in ECP mode. 104 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet SMSC LPC47M182 ...
Page 105
... ECP port transmits this byte to the peripheral automatically. The operation of this register is only defined for the forward direction (direction is 0). Refer to the ECP Parallel Port Forward Timing Diagram, located in the Timing Diagrams section of this datasheet . SMSC LPC47M182 Table 7.4 - ECP Register Definitions ECP MODES ...
Page 106
... In all other modes, Direction is valid and a logic 0 means that the printer port is in output mode (write); a logic 1 means that the printer port is in input mode (read). Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) Advanced I/O Controller with Motherboard GLUE Logic 106 DATASHEET Datasheet SMSC LPC47M182 ...
Page 107
... Data bytes are always read from the head of tFIFO regardless of the value of the direction bit. For example if 44h, 33h, 22h is written to the FIFO, then reading the tFIFO will return 44h, 33h, 22h in the same order as was written. SMSC LPC47M182 107 Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) ...
Page 108
... Enables one of the following 3 cases of interrupts. Once one of the 3 service interrupts has occurred serviceIntr bit shall be set hardware. It must be reset re-enable the interrupts. Writing this bit will not cause an interrupt. Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) Advanced I/O Controller with Motherboard GLUE Logic 108 DATASHEET Datasheet SMSC LPC47M182 ...
Page 109
... All drivers have active pull-ups (push-pull). 111: Configuration Mode. In this mode the confgA, confgB registers are accessible at 0x400 and 0x401. All drivers have active pull-ups (push-pull). Table 7.7 – Programming for Configuration Register B (Bits 5:3) IRQ SELECTED SMSC LPC47M182 Table 7.6 - Extended Control Register MODE CONFIG REG B BITS 5:3 15 ...
Page 110
... Set autoFd = 0, causing the nAutoFd signal to default to the deasserted state. Set mode = 011 (ECP Mode) ECP address/RLE bytes or data bytes may be sent automatically by writing the ecpAFifo or ecpDFifo respectively. Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) Advanced I/O Controller with Motherboard GLUE Logic CONFIG REG B BITS 2:0 011 010 001 000 110 DATASHEET Datasheet SMSC LPC47M182 ...
Page 111
... The ECP port supports run length encoded (RLE) decompression in hardware and can transfer compressed data to a peripheral. Run length encoded (RLE) compression in hardware is not supported. To transfer compressed data in ECP mode, the compression count is written to the ecpAFifo and the data byte is written to the ecpDFifo. SMSC LPC47M182 D7 D[6:0] 0 ...
Page 112
... Parallel Port FIFO mode or ECP Parallel Port Mode. (FIFO test mode will be addressed separately.) Programmed I/O cycle or DMA cycle depending on the selection of DMA or Programmed I/O mode. Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) After a reset, the FIFO is disabled. 112 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet Each data byte is transferred by a SMSC LPC47M182 ...
Page 113
... The ECP requests programmed I/O transfers from the host by activating the interrupt. The programmed I/O will empty or fill the FIFO using the appropriate direction and mode. SMSC LPC47M182 113 Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) DATASHEET ...
Page 114
... Serial IRQ The LPC47M182 supports the serial interrupt to transmit interrupt information to the host system. The serial interrupt scheme adheres to the Serial IRQ Specification for PCI Systems, Version 6.0. Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) (16-<threshold>) free bytes in FIFO ...
Page 115
... SER_IRQ low for a programmable period of three to seven clocks. This makes a total low pulse width of four to eight clocks. Finally, the Host Controller will drive the SER_IRQ back high for one clock, then tri-state. SMSC LPC47M182 START FRAME IRQ0 FRAME IRQ1 FRAME ...
Page 116
... Stop Frames pulse width to determine the next SER_IRQ Cycle’s mode. 7.23.3 SER_IRQ Data Frame Once a Start Frame has been initiated, the LPC47M182 will watch for the rising edge of the Start Pulse and start counting IRQ/Data Frames from there. Each IRQ/Data Frame is three clocks: Sample phase, Recovery phase, and Turn-around phase ...
Page 117
... Interrupt Generating Registers The LPC47M182 contains on-chip Interrupt Generating Registers to enable external software to generate IRQ1 through IRQ15 on the Serial IRQ Interface. These registers, INT_GEN1 and INT_GEN2, are located at offsets 0x1B and 0x1C, respectively, in the in the Power Control Logical Device, when LD_NUM=0, or Runtime Register Block Logical Device, when LD_NUM=1, from the base address setting (set at Index 0x60 and 0x61 Configuration Registers). See “ ...
Page 118
... Serial IRQ stream by writing these bits to ‘0’ overrides other interrupt sources for the Serial IRQ stream. No other functional logic in the LPC47M182 sets bits in these registers. The asserted interrupt in the Serial IRQ stream from registers INT_GEN1 and INT_GEN2 is removed by writing the corresponding bit to ‘1’. ...
Page 119
... This bit read only register. Refer to the description of the Status Register for more information. 7.25.6 CPU-to-Host Communication The LPC47M182 CPU can write to the Output Data register via register DBB. A write to this register automatically sets Bit 0 (OBF) in the Status register. See Table 7.11. ...
Page 120
... If “EN FLAGS” has been executed and P24 is set to a one: the OBF flag is gated onto KIRQ. The KIRQ signal can be connected to system interrupt to signify that the LPC47M182 CPU has written to the output data register via “OUT DBB,A”. If P24 is set to a zero, KIRQ is forced low. On power-up, after a valid RST pulse has been delivered to the device, KIRQ is reset to 0. KIRQ will normally reflects the status of writes “ ...
Page 121
... Table 7.12 shows the contents of the Status register Status Register This register is cleared on a reset. This register is read-only for the Host and read/write by the LPC47M182 CPU. UD Writable by LPC47M182 CPU. These bits are user-definable. SMSC LPC47M182 The oscillator is stopped by disabling the Table 7 ...
Page 122
... There is no output pin associated with this internal signal. OBF (Output Buffer Full) - This flag is set to whenever the LPC47M182 CPU write to the output data register (DBB). When the host system reads the output data register, this bit is automatically reset. ...
Page 123
... If Port 92 is enabled, i.e., bit 2 of KRST_GA20 is set to 1, then a pulse is generated by writing bit 0 of the Port 92 Register and this pulse is AND’ed with the pulse generated from the 8042. This pulse is output on pin nKBDRST and its polarity is controlled by the GPI/O polarity configuration. SMSC LPC47M182 Table 7.14 – Keyboard Port 92 Register NAME ...
Page 124
... KRST_GA20 configuration register Bit 2 nALT_RST Pulse Gen 14us ~ ~ 6us Figure 7.1 – NKBDRST Circuit Table 7.15 – nA20M Truth Table 8042 SYSTEM P21 ALT_A20 nA20M 124 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet nKBDRST SMSC LPC47M182 ...
Page 125
... Advanced I/O Controller with Motherboard GLUE Logic Datasheet 8042 8042 The KLATCH and MLATCH bits are located in the KRST_GA20 register, in Keyboard Logical Device at 0xF0. SMSC LPC47M182 KLATCH Bit VCC D Q KINT CLR RD 60 Figure 7.2 – Keyboard Latch MLATCH Bit VCC D Q MINT ...
Page 126
... PME events. The LPC47M182 has a mode to select the isolation of keyboard and mouse clock and data signals by hardware when the nLPCPD signal is active and/or when the isolation bits are set by software ...
Page 127
... BIOS software needs to clear these PME status bits after power-up. 7.27 General Purpose I/O The LPC47M182 provides a set of flexible Input/Output control functions to the system designer through the 13 independently programmable General Purpose I/O pins (GPIO). The GPIO pins can perform basic I/O and can be individually enabled to generate a PME (except GP24). GPIOs must be programmed as inputs to generate a PME ...
Page 128
... VCC POR VTR POR PME/EETI - Input - - Input PME - Input PME - Input PME - Input PME - Input PME - Input PME - Input PME - Input PME - Hi-Z PME/EETI - Hi-Z PME/EETI - Hi-Z PME - Hi-Z PME GPIO RUNTIME DATA REGISTER REGISTER 1 BIT NO. OFFSET (HEX SMSC LPC47M182 ...
Page 129
... GPIO function and when the pin is configured for the alternate function for all pins, with the exception of the either edge triggered interrupts and DDC functions. The basic GPIO configuration options are summarized in Table 7.18. Table 7.18 – GPIO Configuration Summary SELECTED DIRECTION FUNCTION GPIO SMSC LPC47M182 DATA ALT. FUNC. 2 REGISTER EETI0 EETI1 - - ...
Page 130
... Table 7.19 – GPIO Read/Write Behavior GPIO INPUT PORT LAST WRITE TO GPIO DATA REGISTER BIT PLACED IN GPIO DATA REGISTER 130 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet GPIO Configuration Register bit-0 (Input/Output) GPIO PIN Reading from a GPIO port that is GPIO OUTPUT PORT SMSC LPC47M182 ...
Page 131
... Datasheet 7.27.5 GPIO PME Functionality The LPC47M182 provides 12 GPIOs that can directly generate a PME. See the Table 7.16. The polarity bit in the GPIO control registers select the edge on these GPIO pins that will set the associated status bit in the PME_STS2 and PME_STS3 registers. The default is the low-to-high edge. If the corresponding enable bit in the PME_EN2 and PME_EN3 registers and the PME_EN bit in the PME_EN register is set, a PME will be generated ...
Page 132
... See the “Keyboard and Mouse PME Generation” section for information about using the keyboard and mouse signals to generate a PME. In the LPC47M182 the nIO_PME pin can be programmed open drain, active low, driver. The LPC47M182 nIO_PME pin is fully isolated from other external devices that might pull the nIO_PME signal low ...
Page 133
... The logic will draw no power when disabled. The bit is defined as follows: 0= “Wake on specific key” logic is on (default) 1= “Wake on specific key” logic is off SMSC LPC47M182 FUNCTION Start bit (always 0) Data bit 0 (least significant bit) ...
Page 134
... Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) Advanced I/O Controller with Motherboard GLUE Logic Revolution Time = 60/RPM (sec Pulse Time = (Two Pulses Per Revolution 90kHz (nominal) 134 DATASHEET Datasheet /2 R SMSC LPC47M182 ...
Page 135
... ISPU_400 is defined as: Input with Schmitt Trigger, 400 mV hysteresis, with 30uA internal pull-up. The nHD_LED pin is a logical AND of the inputs nPRIMARY_HD, nSECONDARY_HD and nSCSI used to drive a single color LED. The inputs are internally pulled to VCC. See table below for state definitions. SMSC LPC47M182 Table 7.20 – Hard Drive Front Panel Pins POWER BUFFER ...
Page 136
... DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet OUTPUT nHD_LED NOTES 0 LED On 0 LED On 0 LED On Hi-Z LED Off DESCRIPTION Green Power LED Open-Drain Output Yellow Power LED Open-Drain Output Input from South Bridge for Transitioning to the S5 Power State SMSC LPC47M182 ...
Page 137
... VTR through the 220 ohm resistor to ground. When the LEDs are on, they are powered through the 220 ohm resistor. The following figure shows the recommended external LED circuit. SMSC I/O Figure 7.7 – Example Yellow and Green LED Circuit SMSC LPC47M182 Table 7.23 - LED Truth Table SDY_BLK BIT GRN_LED 0 ...
Page 138
... VCC 3.3mA VTR Table 7.25 – REF5V MAIN SUPPLY REF5V VCC5V < VCC VCC VCC5V > VCC Hi-Z Backdrive Protection SMSC I/O Figure 7.8 – REF5V Circuit 138 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet DESCRIPTION 5V Reference Output Highest System Standby Voltage VCC5V 1k REF5V SMSC LPC47M182 ...
Page 139
... See Figure 13.25 to Figure 13.28 in the “Timing Diagrams” section. 7.32 IDE Reset Output Pin nIDE_RST is an open drain buffered copy of nPCI_RESET. This signal requires an external 1kohm pull-up to VCC5V. This signal will be low when VCC5V=0 since it is externally pulled up to VCC5V. SMSC LPC47M182 Table 7.26 – REF5V_STBY REF5V_STBY VTR Hi-Z Backdrive ...
Page 140
... POWER BUFFER WELL IO_SW VTR 5V DDC Data IOD/ GPIO (Note) IO_SW VTR 5V DDC Clock IOD/ GPIO (Note ) IO_SW VTR 3.3V DDC Data IOD/ GPIO (Note) 140 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet DESCRIPTION 0 Hi-Z DESCRIPTION nPCIRST_OUT2 0 1 DESCRIPTION SMSC LPC47M182 ...
Page 141
... The DDC data pins and the DDC clock pins function as inputs shorted together through the isolation resistor. The DDC signals require external pull-up resistors on LPC47M182. See the “Pins That Require External Resistors” section for resistor values. See Figure 7.10 for recommended schematic implementation ...
Page 142
... Max DDCSDA_5V SEE NOTE 25ohm Max DDCSCL_5V EN GPIO Alternate Function Select bit 142 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet CURRENT ACROSS THE SWITCH No Current flow (0 mA) Current flows from DDCSCL_5V or DDCSCL_3V No Current flow (0 mA) VCC5V 2.2k 2.2k VGA Connector 6.2V 6.2V SMSC LPC47M182 ...
Page 143
... The SMB data pins and the SMB clock pins function as inputs shorted together through the isolation resistor when the switch is closed. The SMBus signals require external pull-up resistors on LPC47M182. See Figure 7.11 for recommended schematic implementation. The switch is controlled by the PWRGD_PS signal. The switch is closed as long as PWRGD_PS is ‘1’. The current flow is controlled by the external signals on the SMB pins ...
Page 144
... Figure 7.11 – SMBUS Isolation Circuit POWER BUFFER WELL OD8 VTR Power Supply Turn-ON Open Drain Output ISPU_400 VTR CPU Present Input from Processor I VTR S3 Power State Input from South Bridge 144 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet VTR 2.7k 2.7k ICH, PCI DESCRIPTION SMSC LPC47M182 ...
Page 145
... Table 7.39 – PWRGD_PLATFORM Truth Table NSLP_S3 PWRGD_PS 1-0 transition level 1-0 transition level 1 0-1 transition 1 0-1 transition 1 0-1 transition A timing diagram for generating the PWRGD_PLATFORM is shown below: SMSC LPC47M182 Table 7.38 – nPS_ON Truth Table INPUTS NSLP_S3 INTERNAL DELAY ELAPSED? PWRGD_PLATFO RM SELECT BIT YES X ...
Page 146
... Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) Figure 7.12 – PRWGD_PLATFORM Generation Table 7.40 – SCK_BJT_GATE Pin POWER BUFFER WELL OD8 VTR Open-Drain Gate Output for the SCK_BJT_GATE in S3 Table 7.41 – SCK_BJT_GATE Truth Table SCK_BJT_GATE (OUTPUT 146 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet DESCRIPTION SMSC LPC47M182 ...
Page 147
... S3 power state. Table 7.43 – nBACKFEED_CUT Truth Table PWRGD_PS SMSC LPC47M182 RMB_SCK V_5P0_STBY 1k SCK_BJT_GATE Figure 7.13 - SCK_BJT_GATE Circuit Buffer Power Well ...
Page 148
... Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) +5VTR 1k SMSC I/O INPUTS NSLP_S5 148 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet +12 1k BACKFEED_CUT +12 1k 470 ohms +5VTR 1k 470 ohms OUTPUT LATCHED_BF_CUT Change (Note) SMSC LPC47M182 ...
Page 149
... Advanced I/O Controller with Motherboard GLUE Logic Datasheet is pulled low a period t1 after nSLP_S5 goes high. The period t1 can be as short as 1msec. Typical measured values are approximately 200msec. The t1 and t2 values are guaranteed by the inherent design of the system and are not controlled by the LPC47M182. V_5P0_STBY nSLP_S3 PWRGD_PS ...
Page 150
... The following figure shows a flowchart of the logic. Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) signal goes high when nBACKFEED_CUT t3 Tpropf Tf MIN 30 1 150 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet goes high and t4 TYP MAX UNITS 250 ms SMSC LPC47M182 then ...
Page 151
... T2) (Verified by ICH) No Yes nSLP_S5 = 1 (Controlled by ICH) nBACKFEED_CUT = 0? (Period T1) No Yes End of Power Up Sequence Main Power Active Figure 7.18 – Latched Backfeed Cut Flowchart SMSC LPC47M182 nBACKFEED_CUT = 1? No Yes LATCHED_BF_CUT = 1 (After Tpropr) nSLP_S5 = nBACKFEED_CUT = 0? Yes LATCHED_BF_CUT = 0 (After Tpropf) 151 Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) ...
Page 152
... IO12 VTR CODEC Down Enable Input/GPIO O12 VTR CODEC Down Reset Output 152 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet DESCRIPTION RESET_DELAY . Note the nRSMRST will be inactive TRIP RESET_FALL . See Table below for timing and voltage DESCRIPTION SMSC LPC47M182 , . Note ...
Page 153
... Note: If GP24 is programmed as GPIO output the GP data bit will also control nCDC_DWN_ENAB input to the CNR logic. This follows the boolean equation: (nAUD_LNK_RST)x( nCDC_DWN_ENAB )=nCDC_DWN_RST nAUD_LNK_RST See Table 13.6 for CNR timing. SMSC LPC47M182 Table 7.49 – CNR Logic Truth Table INPUTS NCDC_DWN_ENAB (NOTE ...
Page 154
... Keyboard Scan Code Tach1 LSB Tach1 MSB Tach2 LSB Tach2 MSB nIO_PME Register MSC_STS Force Disk Change Floppy Data Rate Select Shadow UART1 FIFO Control Shadow Interrupt Generating Register 1 Interrupt Generating Register 2 UART2 FIFO Control Shadow Reserved – reads return 0 SMSC LPC47M182 ...
Page 155
... DESCRIPTION (Type) 0x00 Bit[0] PME_Status = 0 (default) (R/ Set when LPC47M182 would normally assert the nIO_PME signal, independent of the state of the PME_En bit. Bit[7:1] Reserved PME_Status is not affected by Vcc POR, SOFT RESET or HARD RESET. Writing a “1” to PME_Status will clear it and cause the LPC47M182 to stop asserting nIO_PME, in enabled. Writing a “ ...
Page 156
... Bits[7:0] Reserved – reads return 0 (R) 0x0C PME Wake Status Register 3 This register is used to enable individual LPC47M182 (R/W) PME wake sources onto the nIO_PME wake bus. When the PME Wake Enable register bit for a wake source is active (“1”), if the source asserts a wake event so that the associated status bit is “ ...
Page 157
... SMSC LPC47M182 DESCRIPTION (Type) 0x0D PME Wake Enable Register 2 This register is used to enable individual LPC47M182 (R/W) PME wake sources onto the nIO_PME wake bus. When the PME Wake Enable register bit for a wake source is active (“1”), if the source asserts a wake event so that the associated status bit is “ ...
Page 158
... GP21 pin. Bit[1] Either Edge Triggered Interrupt Input 1 Status. This bit is set when an edge occurs on the GP22 pin. Bit[7:2] Reserved. This bit always returns zero. 158 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet SMSC LPC47M182 ...
Page 159
... Default = 0x01 on VCC POR Floppy Data Rate Select Shadow UART1 FIFO Control Shadow INT_GEN1 Default = 0xFF on VCC POR and HARD RESET SMSC LPC47M182 DESCRIPTION (Type) 0x18 Force Disk Change Bit[0] Force Disk Change for FDC0 (R/W) 0=Inactive 1=Active Bit[1] Reserved Force Change 0 can be written to 1 but is not clearable by software ...
Page 160
... Producing an interrupt in the SER_IRQ stream by setting these bits to “0” overrides other interrupt sources for the SER_IRQ stream. No other functional logic in the LPC47M182 sets bits in the register. These bits are only cleared by writing “1” to the bit location. ...
Page 161
... Table 9.1 – GPIO Runtime Registers Summary, LD_NUM = 0 REGISTER TYPE PCI Reset OFFSET (hex R/W - 0D- R R/W - 17- SMSC LPC47M182 VCC POR VTR POR SOFT RESET - 0x01 - - 0x01 - - 0x01 - - 0x01 - - 0x01 - - 0x01 - - 0x01 - - 0x01 - - 0x04 - - 0x04 - - 0x04 - - 0x04 - - 0x05 - - - - - 0x00 - - 0x00 - - - - 161 Revision 1 ...
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... Pull 0x06 General Purpose I/O bit 1.6 Bit[0] In/Out : =1 Input, =0 Output (R/W) Bit[1] Polarity : =1 Invert Invert Bit[2] Alternate Function Select 1=FAN_TACH1 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull 162 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet SMSC LPC47M182 ...
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... Default = 0x04 on VTR POR Note 1 GP22 Default = 0x04 on VTR POR Note 1 GP23 Default = 0x04 on VTR POR Note 1 SMSC LPC47M182 DESCRIPTION (Type) 0x07 General Purpose I/0 bit 1.7 Bit[0] In/Out : =1 Input, =0 Output (R/W) Bit[1] Polarity :=1 Invert Invert Bit[2] Alternate Function Select 1=FAN_TACH2 0=GPIO Bits[6:3] Reserved ...
Page 164
... Bit[4] GP14 Bit[5] GP15 Bit[6] GP16 Bit[7] GP17 0x16 General Purpose I/O Data Register 2 Bit[0] GP20 (R/W) Bit[1] GP21 Bit[2] GP22 Bit[3] GP23 Bit[4] GP24 Bits[7:5] Reserved Bits[7:0] Reserved – reads return 0 (R) 164 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet SMSC LPC47M182 ...
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... R/W 0x01 R/W 0xFF 1C R/W 0xFF R/W - SMSC LPC47M182 SOFT VCC POR VTR POR RESET - 0x00 - - - - - 0x00 - - - - - 0x00 - - 0x00 - - 0x00 - - - - - 0x00 - - 0x00 - - 0x00 - - - - - 0x03 - - 0x00 - - 0x00 - - 0x00 - - 0x00 - - 0x00 - - 0x80 - - 0x00 ...
Page 166
... Advanced I/O Controller with Motherboard GLUE Logic SOFT VCC POR VTR POR RESET - 0x01 - - 0x01 - - 0x04 - - 0x04 - - 0x04 - - 0x04 - - 0x05 - - - - - 0x00 - - 0x00 - - - - 166 DATASHEET Datasheet REGISTER GP16 GP17 GP20 GP21 GP22 GP23 GP24 Reserved – reads return 0 GP1 GP2 Reserved – reads return 0 SMSC LPC47M182 ...
Page 167
... System Elements 11.1.1 Primary Configuration Address Decoder After a hard reset (nPCI_RESET pin asserted) or Vcc Power On Reset the LPC47M182 is in the Run Mode with all logical devices disabled. The logical devices may be configured through two standard Configuration I/O Ports (INDEX and DATA) by placing the LPC47M182 into Configuration Mode. ...
Page 168
... To exit the Configuration State the system writes 0xAA to the CONFIG PORT. The chip returns to the RUN State. Note: Only two states are defined (Run and Configuration). In the Run State the chip will always be ready to enter the Configuration State. Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) 168 DATASHEET Datasheet SMSC LPC47M182 ...
Page 169
... LD_NUM Bit The LD_NUM bit in the TEST 7 global configuration register (0x29) is used to select between the logical device numbering in the LPC47M182. See the TEST 7 register for LD_NUM bit description. Table 11.1 and Table 11.2 summarize the logical device registers when LD_NUM bit is 0 and 1. ...
Page 170
... Table 11.1– LPC47M182 Configuration Registers Summary, LD_NUM bit = 0 INDEX TYPE PCI RESET 0x02 W 0x00 0x03 R - 0x07 R/W 0x00 0x20 R 0x74 0x21 R - 0x22 R/W 0x00 0x23 R - 0x24 R/W 0x44 0x2E 0x26 R/W 0x00 0x27 R/W 0x28 R/W - 0x29 R/W 0x00 0x2A R/W - 0x2B R/W - 0x2C R/W - 0x2D R/W - 0x2E R/W - 0x2F R/W - LOGICAL DEVICE 0 CONFIGURATION REGISTERS (FDD) ...
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... LOGICAL DEVICE 7 CONFIGURATION REGISTERS (GPIO) 0x00 0x30 R/W 0x00 0x60 R/W 0x00 0x61 R/W Note: Reserved registers are read-only, reads return 0. Note 1. Bits[7:5] of this register reset on VTR POR only. SMSC LPC47M182 SOFT VCC POR VTR POR RESET 0x00 0x00 0x00 0x00 0x00 0x00 0x00 ...
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... Table 11.2 – LPC47M182 Configuration Register Summary, LD_NUM bit = 1 INDEX TYPE PCI RESET 0x02 W 0x00 0x03 R - 0x07 R/W 0x00 0x20 R 0x74 0x21 R - 0x22 R/W 0x00 0x23 R - 0x24 R/W 0x44 0x2E 0x26 R/W 0x00 0x27 R/W 0x28 R/W - 0x29 R/W 0x01 0x2A R/W - 0x2B R/W - 0x2C R/W - 0x2D R/W - 0x2E R/W - 0x2F R/W - LOGICAL DEVICE 0 CONFIGURATION REGISTERS (FDD) ...
Page 173
... R/W LOGICAL DEVICE B CONFIGURATION REGISTERS (Reserved) LOGICAL DEVICE C CONFIGURATION REGISTERS (Reserved) Note: Reserved registers are read-only, reads return 0. Note 1. Bits[7:6, 5 and 1] of KRESET and GateA20 Select register reset on VTR POR only. SMSC LPC47M182 SOFT VCC POR VTR POR RESET 0x02 0x02 ...
Page 174
... CHIP LEVEL, SMSC DEFINED 0x20 R A read only register which provides device identification. Bits[7:0] = 0x74 when read. 0x21 R A read only register which provides device revision information. Bits[7:0] = current revision when read. 174 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet SMSC LPC47M182 ...
Page 175
... Configuration Address Byte 1 Default = 0x00 on VCC POR and HARD RESET TEST 8 Default = 0x00 on VCC POR and VTR POR SMSC LPC47M182 ADDRESS DESCRIPTION CHIP (GLOBAL) CONTROL REGISTERS 0x22 R/W Bit[0] FDC Power Bit[1] Reserved Bit[2] Reserved Bit[3] Parallel Port Power Bit[4] Serial Port 1 Power ...
Page 176
... Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results. 0x2E R/W Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results. 176 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet SMSC LPC47M182 ...
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... VCC POR, VTR POR, HARD RESET and SOFT RESET Logical Device Control Logical Device Control Memory Base Address SMSC LPC47M182 ADDRESS DESCRIPTION CHIP (GLOBAL) CONTROL REGISTERS 0x2F R/W Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results. ...
Page 178
... Reserved - not implemented. These register locations ignore writes and return zero when read. (0xE0-0xFE) Reserved – Vendor Defined (see SMSC defined Logical Device Configuration Registers). 0xFF Reserved 178 DATASHEET Datasheet SMSC LPC47M182 ...
Page 179
... DMA Channel 0x74 (R/W) Select Default=0x02 or 0x04 (Note 1) on VCC POR, VTR POR, HARD RESET and SOFT RESET SMSC LPC47M182 DEFINITION Bits[3:0] selects which interrupt is used for the primary Interrupt. 0x00= no interrupt selected 0x01= IRQ1 0x02= IRQ2 0x03= IRQ3 0x04= IRQ4 0x05= IRQ5 ...
Page 180
... D. Keyboard Controller: Refer to the KBD section of this spec. Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) Advanced I/O Controller with Motherboard GLUE Logic IRQ CONTROLLED BY PRINTER IRQE SPP IRQE FIFO (on) ECP (on) EPP IRQE RES IRQE TEST (on) CONFIG IRQE 180 DATASHEET Datasheet DMA CONTROLLED BY dmaEn dmaEn dmaEn dmaEn dmaEn dmaEn dmaEn dmaEn SMSC LPC47M182 ...
Page 181
... Serial Port 2 0x60,0x61 0x03 Serial Port 0x60,0x61 0x04 Power Control 0x60,0x61 0x05 Mouse n/a 0x06 KYBD n/a 0x07 GPIO 0x60,0x61 SMSC LPC47M182 BASE I/O RANGE (NOTE 1) [0x0100:0x0FF8 SRA +1 : SRB ON 8 BYTE BOUNDARIES +2 : DOR +3 : TSR +4 : MSR/DSR +5 : FIFO +7 : DIR/CCR [0x0100:0x0FFC Data/ecpAfifo ON 4 BYTE BOUNDARIES +1 : Status (EPP Not supported) ...
Page 182
... EPP Data EPP Data 3 [0x0100:0x0FF8 RB/TB/LSB div +1 : IER/MSB div ON 8 BYTE BOUNDARIES +2 : IIR/FCR +3 : LCR +4 : MSR +5 : LSR +6 : MSR +7 : SCR n/a n/a n/a n/a Not Relocatable +0 : Data Register Fixed Base Address: 60, Command/Status Reg. 182 DATASHEET Datasheet FIXED BASE OFFSETS FIXED BASE OFFSETS SMSC LPC47M182 ...
Page 183
... SMSC Defined Logical Device Configuration Registers The SMSC Specific Logical Device Configuration Registers reset to their default values only on hard resets generated by Vcc or VTR POR (as shown) or the nPCI_RESET signal. These registers are not affected by soft resets. SMSC LPC47M182 BASE I/O RANGE (NOTE 1) n/a n/a ...
Page 184
... Bit[5] Reserved, set to zero Bit[6] FDC Output Type Control = 0 FDC outputs are OD12 open drain (default FDC outputs are O12 push-pull Bit[7] FDC Output Control = 0 FDC outputs active (default FDC outputs tri-stated 184 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet SMSC LPC47M182 ...
Page 185
... Default = 0xFF on VCC POR, VTR POR and HARD RESET FDD0 Default = 0x00 on VCC POR, VTR POR and HARD RESET SMSC LPC47M182 DEFINITION 0xF1 R/W Note: Bits[ this register are mapped to 0xF8 register. Bit[0] Forced Write Protect = 0 Inactive (default FDD nWRTPRT input is forced active when either of the drives has been selected ...
Page 186
... Normal (default) Bit[6] Floppy Mode. This bit maps to Bit[0] Floppy Mode in the FDC Mode Register (0xF0 Normal Floppy Mode (default Enhanced Floppy Mode 2 (OS2) Bit[7] Reserved 186 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet SMSC LPC47M182 ...
Page 187
... IR Option Register Default = 0x02 on VCC POR, VTR POR and HARD RESET IR Half Duplex Timeout Default = 0x03 on VCC POR, VTR POR and HARD RESET SMSC LPC47M182 REG DEFINITION INDEX 0xF0 R/W Bit[0] MIDI Mode = 0 MIDI support disabled (default MIDI support enabled Bit[1] High Speed ...
Page 188
... Bits[3:0] Parallel Port Mode. The Bits[3:1] map directly to Bits[2:0] in the PP Mode Register (0xF0). = 0001 Standard and Bi-directional (SPP) Mode = 0010 EPP-1.9 and SPP Mode = 0100 ECP Mode = 1000 Printer Mode (default) = others Reserved Bits[7:4] Reserved 188 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet SMSC LPC47M182 ...
Page 189
... Configure UART2 (or UART1) to use No IRQ selected. 3. Set the share IRQ bit. Note: If both UARTs are configured to use different IRQs and the share IRQ bit is set, then both of the UART IRQs will assert when either UART generates an interrupt. SMSC LPC47M182 REG DEFINITION INDEX ...
Page 190
... MINT is the latched 8042 MINT Bit[3] KLATCH = 0 KINT is the 8042 KINT ANDed with Latched KINT (default KINT is the latched 8042 KINT Bit[2] Port 92 Select = 0 Port 92 Disabled = 1 Port 92 Enabled Bit[1] Reserved Bit[0] Reserved 190 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet SMSC LPC47M182 ...
Page 191
... NAME CLOCKI32 Default = 0x00 on VTR POR INT_G Default = 0x00 on VCC POR, VTR POR, HARD RESET and SOFT RESET SMSC LPC47M182 REG DEFINITION INDEX 0xF0 Bit[0] (CLK32_PRSN) (R/W) 0=32kHz clock is connected to the CLKI32 pin (default) 1=32kHz clock is not connected to the CLKI32 pin (pin is grounded) Bit[1] SPEKEY_EN. This bit is used to turn the logic for the “ ...
Page 192
... MAX V 0 2 2 2.2 5.5 IH 250 HYS 192 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet + +150 UNITS COMMENTS V TTL Levels V TTL Levels V TTL Levels V TTL Levels uA V Schmitt Trigger V Schmitt Trigger mV SMSC LPC47M182 ...
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... Low Output Level High Output Level V For REF5V_STBY Low Output Level High Output Level V O8 Output Buffer Low Output Level High Output Level V OD8 Output Buffer Low Output Level High Output Level V SMSC LPC47M182 MIN TYP MAX V 0 2.2 5.5 IH 400 HYS V 0.8 ...
Page 194
... Advanced I/O Controller with Motherboard GLUE Logic Datasheet UNITS COMMENTS 12mA -6mA 12mA OL V Open-Drain 14mA -14mA 24mA OL V Open-Drain V TTL Levels V TTL Levels 8mA -4mA OH V Schmitt Trigger V Schmitt Trigger 8mA -4mA OH SMSC LPC47M182 ...
Page 195
... IO_SW Input/Output Pins of this type are connected in pairs through a switch. The switch provides a 25 ohm (max) resistance to ground when closed. See SMBus Isolation Circuitry and Special Type Voltage Translation Circuit sections for a description. Note: Vcc=5V max. SMSC LPC47M182 MIN TYP MAX V 0.8 ...
Page 196
... Advanced I/O Controller with Motherboard GLUE Logic UNITS COMMENTS V TTL Levels V TTL Levels 24mA OL V Open-Drain Vcc Vcc Vcc and 3.3V CC µ 3.6V Max IN µ µ 5.5V Max IN µ SMSC LPC47M182 Datasheet ...
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... Standby Power Requirements This includes only signals that are outputs and source standby current (no OD outputs). Internal pull-ups are ignored due to their small contribution. External pull-ups are not in this analysis because they do not cause LPC47M182 to draw a discernable amount of additional power. SYMBOL REF5V_STBY ...
Page 198
... The input capacitance of a port is measured at the connector pins. Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) LIMITS SYMBOL MIN TYP MAX OUT 198 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet UNIT TEST CONDITION pF All pins except pin under test tied ground pF SMSC LPC47M182 ...
Page 199
... For the Timing Diagrams shown, the following capacitive loads are used on outputs. SER_IRQ LAD [3:0] nLDRQ PD[0:7] nSTROBE YLW_LED GRN_LED nIDE_RSTDRV nPCIRST_OUT nPCIRST_OUT2 PS_ON SCK_BJT_GATE PWRGD_PLATFORM nCDC_DWN_ENAB/ nCDC_DWN_RST SMSC LPC47M182 CAPACITANCE TOTAL (pF) NAME nDIR 240 nSTEP 240 nDS0 240 240 240 nALF ...
Page 200
... All Host Accesses After Powerup (Note 1) Note 1: Internal write-protection period after Vcc passes 2.7 volts on power-up Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) Advanced I/O Controller with Motherboard GLUE Logic Figure 13.1 - Power-Up Timing MIN 300 100 125 200 DATASHEET Datasheet t 3 TYP MAX UNITS us us 500 us SMSC LPC47M182 ...