LPC47M182-NR SMSC [SMSC Corporation], LPC47M182-NR Datasheet - Page 142
LPC47M182-NR
Manufacturer Part Number
LPC47M182-NR
Description
ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
Manufacturer
SMSC [SMSC Corporation]
Datasheet
1.LPC47M182-NR.pdf
(223 pages)
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GPIO/EETI/Reserved
DDC (DEFAULT)
DDC (DEFAULT)
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
FUNCTION SELECT
DDC Vs. GPIO
ALTERNATE
NOTE: The switch is implemented as an n-channel switch that will not pass a full voltage swing.
It provides a current path to ground.
The board designer should treat each signal pair to the switch as a separate bus with a
resistance in the path.
The maximum resistance of the switch between any bus to any other bus is 25ohms (when the
switch is on). When the switch is off the impedance is Hi-Z and the current is zero.
The design requires pull-ups on each of the busses shown above.
It is recommended that the pullups be selected so that the total maximum current on both
busses does not exceed 2mA to limit the voltage drop across the switch.
BIT/S
MCH
DDCSDA_3V
DDCSCL_3V
Don’t Care
0V
3.6V (max)
Table 7.33 – VGA DDCSCL Voltage Translation Logic
DDCSCL_3V
Figure 7.10 – VGA DDC Voltage Translation Circuit
4.7k
VCC
4.7k
DATASHEET
GPIO Alternate
Don’t Care
0V
5.5V (max)
LPC47M182
25ohm
25ohm
SEE NOTE
Max
Max
Select bit
Function
EN
DDCSCL_5V
142
DDCSDA_5V
DDCSCL_5V
Advanced I/O Controller with Motherboard GLUE Logic
No Current flow (0 mA)
Current flows from DDCSCL_5V or
DDCSCL_3V
No Current flow (0 mA)
CURRENT ACROSS THE SWITCH
6.2V
2.2k
VCC5V
2.2k
6.2V
Connector
VGA
SMSC LPC47M182
Datasheet
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