LPC47M182-NR SMSC [SMSC Corporation], LPC47M182-NR Datasheet - Page 16
LPC47M182-NR
Manufacturer Part Number
LPC47M182-NR
Description
ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
Manufacturer
SMSC [SMSC Corporation]
Datasheet
1.LPC47M182-NR.pdf
(223 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC47M182-NR
Manufacturer:
SMSC
Quantity:
1
Part Number:
LPC47M182-NR
Manufacturer:
SMSC
Quantity:
20 000
- Current page: 16 of 223
- Download datasheet (2Mb)
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
17
18
19
20
21
22
23
24
25
PIN#
nDIR
nDS0
nMTR0
nINDEX
DRVDEN1
DRVDEN0
nDCD1
nDSR1
RXD1
(NOTE 1)
NAME
Step Direction Output. This high current
low active output determines the direction
of the head movement. A logic “1” on this
pin means outward motion, while a logic
“0” means inward motion. Can be
configured as an Open-Drain Output.
Drive Select 0 Output. Can be configured
as an Open-Drain Output.
Motor On 0 Output. Can be configured as
an Open-Drain Output.
This active low Schmitt Trigger input
senses from the disk drive that the head
is positioned over the beginning of a
track, as marked by an index hole.
Drive Density Select 1 Output. Indicates
the drive and media selected. Can be
configured as Open-Drain Output.
Drive Density Select 0 Output. Indicates
the drive and media selected. Can be
configured as Open-Drain Output.
Active low Data Carrier Detect input for
the serial port. Handshake signal that
notifies the UART that carrier signal is
detected by the modem. The CPU can
monitor the status of nDCD signal by
reading bit 7 of Modem Status Register
(MSR). A nDCD signal state change from
low to high after the last MSR read will set
MSR bit 3 to a 1. If bit 3 of Interrupt
Enable Register is set, the interrupt is
generated when nDCD changes state.
Note: Bit 7 of MSR is the complement of
nDCD.
Active low Data Set Ready input for the
serial port. Handshake signal that notifies
the UART that the modem is ready to
establish the communication link. The
CPU can monitor the status of nDSR
signal by reading bit 5 of Modem Status
Register (MSR). A nDSR signal state
change from low to high after the last
MSR read will set MSR bit 1 to a 1. If bit
3 of Interrupt Enable Register is set, the
interrupt is generated when nDSR
changes state.
Note: Bit 5 of MSR is the complement of
nDSR.
Receiver serial data input.
SERIAL PORT 1 INTERFACE (8)
DESCRIPTION
DATASHEET
16
O12
O12
O12
IS
O12
O12
I
I
IS
Advanced I/O Controller with Motherboard GLUE Logic
(NOTE 2)
BUFFER
NAME
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
(NOTE 3)
WELL
PWR
SMSC LPC47M182
NOTES
Datasheet
Related parts for LPC47M182-NR
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
FAST ETHERNET PHYSICAL LAYER DEVICE
Manufacturer:
SMSC Corporation
Datasheet:
Part Number:
Description:
357-036-542-201 CARDEDGE 36POS DL .156 BLK LOPRO
Manufacturer:
SMSC Corporation
Datasheet:
Part Number:
Description:
357-036-542-201 CARDEDGE 36POS DL .156 BLK LOPRO
Manufacturer:
SMSC Corporation
Datasheet:
Part Number:
Description:
357-036-542-201 CARDEDGE 36POS DL .156 BLK LOPRO
Manufacturer:
SMSC Corporation
Datasheet:
Part Number:
Description:
4-PORT USB2.0 HUB CONTROLLER
Manufacturer:
SMSC Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
SMSC Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
SMSC Corporation
Datasheet:
Part Number:
Description:
FDC37C672ENHANCED SUPER I/O CONTROLLER WITH FAST IR
Manufacturer:
SMSC Corporation
Datasheet:
Part Number:
Description:
COM90C66LJPARCNET Controller/Transceiver with AT Interface and On-Chip RAM
Manufacturer:
SMSC Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
SMSC Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
SMSC Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
SMSC Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
SMSC Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
SMSC Corporation
Datasheet: