MC68HC908AS60MFN MOTOROLA [Motorola, Inc], MC68HC908AS60MFN Datasheet - Page 335
![no-image](/images/no-image-200.jpg)
MC68HC908AS60MFN
Manufacturer Part Number
MC68HC908AS60MFN
Description
HCMOS Microcontroller Unit
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC908AS60MFN.pdf
(454 pages)
- Current page: 335 of 454
- Download datasheet (6Mb)
21.5 BDLC MUX Interface
21.5.1 Rx Digital Filter
MC68HC908AS60 — Rev. 1.0
MOTOROLA
The MUX interface is responsible for bit encoding/decoding and digital
noise filtering between the protocol handler and the physical interface.
The receiver section of the BDLC includes a digital low-pass filter to
remove narrow noise pulses from the incoming message. An outline of
the digital filter is shown in
INTERFACE
INTERFACE
PHYSICAL
Freescale Semiconductor, Inc.
Rx DATA
(BDRxD)
CLOCK
FROM
MUX
For More Information On This Product,
Byte Data Link Controller-Digital (BDLC-D)
Figure 21-5. BDLC Rx Digital Filter Block Diagram
Go to: www.freescale.com
D
INPUT
SYNC
Figure 21-4. BDLC Block Diagram
Q
UP/DOWN
Figure
4-BIT UP/DOWN COUNTER
PHYSICAL INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
CPU INTERFACE
TO J1850 BUS
TO CPU
21-5.
Byte Data Link Controller-Digital (BDLC-D)
OUT
BDLC
D
LATCH
DATA
BDLC MUX Interface
Q
Technical Data
Rx DATA OUT
FILTERED
335
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