HD6413008F RENESAS [Renesas Technology Corp], HD6413008F Datasheet - Page 255
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HD6413008F
Manufacturer Part Number
HD6413008F
Description
Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6413008F.pdf
(686 pages)
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5. Set the STR bit to 1 in TSTR to start the timer counter.
• Free-running and periodic counter operation
A reset leaves the counters (16TCNTs) in 16-bit timer channels 0 to 2 all set as free-running
counters. A free-running counter starts counting up when the corresponding bit in TSTR is set
to 1. When the count overflows from H'FFFF to H'0000, the OVF flag is set to 1 in TISRC.
After the overflow, the counter continues counting up from H'0000. Figure 8.13 illustrates
free-running counting.
When a channel is set to have its counter cleared by compare match, in that channel 16TCNT
operates as a periodic counter. Select the output compare function of GRA or GRB, set bit
CCLR1 or CCLR0 in 16TCR to have the counter cleared by compare match, and set the count
period in GRA or GRB. After these settings, the counter starts counting up as a periodic
counter when the corresponding bit is set to 1 in TSTR. When the count matches GRA or
GRB, the IMFA or IMFB flag is set to 1 in TISRA/TISRB and the counter is cleared to
H'0000. If the corresponding IMIEA or IMIEB bit is set to 1 in TISRA/TISRB, a CPU
interrupt is requested at this time. After the compare match, 16TCNT continues counting up
from H'0000. Figure 8.14 illustrates periodic counting.
H'FFFF
H'0000
STR0 to
STR2 bit
OVF
16TCNT value
Figure 8.13 Free-Running Counter Operation
Rev.4.00 Aug. 20, 2007 Page 211 of 638
REJ09B0395-0400
8. 16-Bit Timer
Time
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