HD6417616 RENESAS [Renesas Technology Corp], HD6417616 Datasheet - Page 270

• Manufacturer Part Number: HD6417616
• Description: 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 6 User Break Controller (UBC)
B. Register settings: BARA = H'00027128 / BAMRA = H'00000000 / BBRA = H'005A
C. Register settings: BBRA = H'0000
Rev. 2.00 Mar 09, 2006 page 244 of 906
REJ09B0292-0200
Set conditions:
On channel A, a user break interrupt is not generated as an instruction fetch is not a write
cycle.
On channel B, a user break interrupt is not generated as an instruction fetch is performed on an
even address.
A user break interrupt is generated by a channel C and D sequential condition match before
execution of the instruction at address H'0003722E following execution of the instruction at
address H'00037226.
BARB = H'00031415 / BAMRB = H'00000000 / BBRB = H'0054
BARC = H'00037226 / BAMRC = H'00000000 / BBRC = H'0056
BDRC = H'00000000 / BDMRC = H'00000000
BARD = H'0003722E / BAMRD = H'00000000 / BBRD = H'0056
BDRD = H'00000000 / BDMRD = H'00000000
BRCR = H'00080000
Channels A and B independent, channel C
Channel A: Address:
Channel B: Address:
Channel C: Address:
Channel D: Address:
BBRB = H'0000
BARC = H'00037226 / BAMRC = H'00000000 / BBRC = H'005A
BDRC = H'00000000 / BDMRC = H'00000000
BARD = H'0003722E / BAMRD = H'00000000 / BBRD = H'0056
BDRD = H'00000000 / BDMRD = H'00000000
BRCR = H'00080000
Bus cycle: CPU, instruction fetch (pre-execution), write, word
Bus cycle: CPU, instruction fetch (pre-execution),
Data:
Bus cycle: CPU, instruction fetch (pre-execution), read, word
Data:
Bus cycle: CPU, instruction fetch (pre-execution), read, word
H'00027128; address mask: H'00000000
H'00031415; address mask: H'00000000
read (operand size not included in conditions)
H'00037226; address mask: H'00000000
H'00000000; data mask: H'00000000
H'0003722E; address mask: H'00000000
H'00000000; data mask: H'00000000
channel D sequential mode