HD6417616 RENESAS [Renesas Technology Corp], HD6417616 Datasheet - Page 576

• Manufacturer Part Number: HD6417616
• Description: 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 13 Watchdog Timer (WDT)
Reading from WTCNT, WTCSR, and RSTCSR: WTCNT, WTCSR, and RSTCSR are read
like other registers. Use byte transfer instructions. The read addresses are H'FFFFFE80 for
WTCSR, H'FFFFFE81 for WTCNT, and H'FFFFFE83 for RSTCSR.
13.3
13.3.1
To use the WDT as a watchdog timer, set the WT/IT and TME bits in WTCSR to 1. Software
must prevent WTCNT overflow by rewriting the WTCNT value (normally by writing H'00) before
overflow occurs. Thus, WTCNT will not overflow while the system is operating normally, but if
WTCNT fails to be rewritten and overflows occur due to a system crash or the like, a WDTOVF
signal is output (figure 13.4). The WDTOVF signal can be used to reset the system. The
WDTOVF signal is output for 512 clock cycles.
If the RSTE bit in RSTCSR is set to 1, a signal to reset the chip will be generated internally
simultaneously with the WDTOVF signal when WTCNT overflows. Either a power-on reset or a
manual reset can be selected by the RSTS bit. The internal reset signal is output for 2048 clock
cycles.
If a reset due to the input signal from the RES pin and a reset due to WDT overflow occur
simultaneously, the RES reset takes priority and the WOVF bit in RSTCSR is cleared to 0.
Rev. 2.00 Mar 09, 2006 page 550 of 906
REJ09B0292-0200
Writing 0 to the WOVF bit
Address:
Writing to the RSTE and RSTS bits
Address:
Operation
Operation in Watchdog Timer Mode
H'FFFFFE82
H'FFFFFE82
Figure 13.3 Writing to RSTCSR
15
15
H'A5
H'5A
8 7
8 7
Write data
H'00
0
0