HD6417616 RENESAS [Renesas Technology Corp], HD6417616 Datasheet - Page 648

• Manufacturer Part Number: HD6417616
• Description: 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 14 Serial Communication Interface with FIFO (SCIF)
Rev. 2.00 Mar 09, 2006 page 622 of 906
REJ09B0292-0200
Figure 14.22 Sample Flowchart for Serial Data Transmission and Reception
No
No
No
from SCFRDR, and clear RDF
Read ORER flag in SC2SSR
to SCFTDR and clear TDRE
Read TDFE flag in SC1SSR
Read RDF flag in SC1SSR
Clear TE and RE bits to 0
Start of transmission/
flag to 0 in SC1SSR
flag to 0 in SC1SSR
All data transferred?
End of transmission/
Write transmit data
Read receive data
Initialization
ORER = 1?
TDFE = 1?
in SCSCR
RDF = 1?
reception
reception
No
Yes
Yes
Yes
Error handling
Yes
1
2
4
5
3
1. PFC initialization: Set the TxD and
2. SCIF status check and transmit data
3. Receive error handling: If a receive
4. SCIF status check and receive data
5. Serial transmission/reception
Note: When switching from transmitting
RxD pins, and the SCK pin if
necessary, with the PFC.
write: Read SC1SSR and check that
the TDFE flag is set to 1, then write
transmit data to SCFTDR and clear
the TDFE flag to 0. Transition of the
TDFE flag from 0 to 1 can also be
identified by a TXI interrupt.
error occurs, read the ORER flag in
SC2SSR, and after performing the
appropriate error handling, clear the
ORER flag to 0.
Transmission/reception cannot be
resumed if the ORER flag is set to 1.
read: Read SC1SSR and check that
the RDF flag is set to 1, then read
receive data from SCFRDR and
clear the RDF flag to 0. Transition of
the RDF flag from 0 to 1 can also be
identified by an RXI interrupt.
continuation procedure: To continue
serial transmission/reception, finish
reading the RDF flag, reading
SCFRDR, and clearing the RDF flag
to 0, before the MSB (bit 7) of the
current frame is received. Also,
before the MSB (bit 7) of the current
frame is transmitted, read 1 from the
TDFE flag to confirm that writing is
possible, then write data to SCFTDR
and clear the TDFE flag to 0.
or receiving to simultaneous
transmitting and receiving, first
clear the TE bit and RE bit to 0,
then set the TE bit and RE bit to
1 simultaneously.