HD6417616 RENESAS [Renesas Technology Corp], HD6417616 Datasheet - Page 492

• Manufacturer Part Number: HD6417616
• Description: 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 11 Direct Memory Access Controller (DMAC)
11.2
11.2.1
DMA source address registers 0 and 1 (SAR0 and SAR1) are 32-bit read/write registers that
specify the source address of a DMA transfer. During a DMA transfer, these registers indicate the
next source address. (In single-address mode, SAR is ignored in transfers from external devices
with DACK to memory-mapped external devices or external memory). In 16-byte unit transfers,
always set the value of the source address to a 16-byte boundary (16n address). Operation results
cannot be guaranteed if other values are used. Transmission in 16-byte units can be set only in
auto-request mode and at edge detection in external request mode. Values are retained in a reset, in
standby mode, and when the module standby function is used.
11.2.2
DMA destination address registers 0 and 1 (DAR0 and DAR1) are 32-bit read/write registers that
specify the destination address of a DMA transfer. During a DMA transfer, these registers indicate
the next destination address. (In single-address mode, DAR is ignored in transfers from memory-
mapped external devices or external memory to external devices with DACK). In 16-byte unit
transfers, always set the value of the source address to a 16-byte boundary (16n address).
Operation results cannot be guaranteed if other values are used. Transmission in 16-byte units can
be set only in auto-request mode and at edge detection in external request mode. Values are
retained in a reset, in standby mode, and when the module standby function is used.
If synchronous DRAM is accessed when performing 16-byte-unit transfer, a 16-byte boundary
(address 16n) value must be set for the destination address.
Rev. 2.00 Mar 09, 2006 page 466 of 906
REJ09B0292-0200
Initial value:
Initial value:
Register Descriptions
DMA Source Address Registers 0 and 1 (SAR0, SAR1)
DMA Destination Address Registers 0 and 1 (DAR0, DAR1)
R/W:
R/W:
Bit:
Bit:
R/W
R/W
31
31
—
—
R/W
R/W
30
30
—
—
R/W
R/W
29
29
—
—
…
…
…
…
…
…
…
…
R/W
R/W
—
—
3
3
R/W
R/W
—
—
2
2
R/W
R/W
—
—
1
1
R/W
R/W
—
—
0
0